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fix minor things discovered through a deep walk-through #212

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Merged
merged 2 commits into from
Nov 29, 2023
Merged

fix minor things discovered through a deep walk-through #212

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56adc96
fix minor things discovered through a deep walk-through
leekillough Nov 23, 2023
f700382
remove duplicated decode code
leekillough Nov 24, 2023
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13 changes: 8 additions & 5 deletions common/include/RevCommon.h
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@
#include <functional>
#include <ostream>
#include <type_traits>
#include <utility>

#ifndef _REV_NUM_REGS_
#define _REV_NUM_REGS_ 32
Expand Down Expand Up @@ -90,20 +91,22 @@ inline uint64_t make_lsq_hash(uint16_t destReg, RevRegClass regType, unsigned Ha

struct MemReq{
MemReq() = default;
MemReq(const MemReq&) = default;
MemReq& operator=(const MemReq&) = default;
~MemReq() = default;

MemReq(uint64_t addr, uint16_t dest, RevRegClass regclass,
unsigned hart, MemOp req, bool outstanding, std::function<void(MemReq)> func) :
Addr(addr), DestReg(dest), RegType(regclass), Hart(hart),
ReqType(req), isOutstanding(outstanding), MarkLoadComplete(func)
ReqType(req), isOutstanding(outstanding), MarkLoadComplete(std::move(func))
{
}

void Set(uint64_t addr, uint16_t dest, RevRegClass regclass, unsigned hart, MemOp req, bool outstanding,
std::function<void(MemReq)> func)
void Set(uint64_t addr, uint16_t dest, RevRegClass regclass, unsigned hart,
MemOp req, bool outstanding, std::function<void(MemReq)> func)
{
Addr = addr; DestReg = dest; RegType = regclass; Hart = hart;
ReqType = req; isOutstanding = outstanding;
MarkLoadComplete = func;
ReqType = req; isOutstanding = outstanding; MarkLoadComplete = std::move(func);
}

uint64_t Addr = _INVALID_ADDR_;
Expand Down
3 changes: 1 addition & 2 deletions include/RevHart.h
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Expand Up @@ -42,8 +42,7 @@ class RevHart{
///< RevHart: Constructor
RevHart(unsigned ID, const std::shared_ptr<std::unordered_map<uint64_t, MemReq>>& LSQueue,
std::function<void(const MemReq&)> MarkLoadCompleteFunc)
: ID(ID), LSQueue(LSQueue), MarkLoadCompleteFunc(MarkLoadCompleteFunc) {}

: ID(ID), LSQueue(LSQueue), MarkLoadCompleteFunc(std::move(MarkLoadCompleteFunc)) {}

///< RevHart: Destructor
~RevHart() = default;
Expand Down
8 changes: 4 additions & 4 deletions include/RevInstHelpers.h
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Expand Up @@ -77,7 +77,7 @@ bool load(RevFeature *F, RevRegFile *R, RevMem *M, RevInst Inst) {
MemOp::MemOpREAD,
true,
R->GetMarkLoadComplete());
R->LSQueueInsert({make_lsq_hash(Inst.rd, RevRegClass::RegGPR, F->GetHartToExecID()), req});
R->LSQueue->insert({make_lsq_hash(Inst.rd, RevRegClass::RegGPR, F->GetHartToExecID()), req});
M->ReadVal(F->GetHartToExecID(),
rs1 + Inst.ImmSignExt(12),
reinterpret_cast<std::make_unsigned_t<T>*>(&R->RV32[Inst.rd]),
Expand All @@ -95,14 +95,14 @@ bool load(RevFeature *F, RevRegFile *R, RevMem *M, RevInst Inst) {
MemOp::MemOpREAD,
true,
R->GetMarkLoadComplete());
R->LSQueueInsert({make_lsq_hash(Inst.rd, RevRegClass::RegGPR, F->GetHartToExecID()), req});
R->LSQueue->insert({make_lsq_hash(Inst.rd, RevRegClass::RegGPR, F->GetHartToExecID()), req});
M->ReadVal(F->GetHartToExecID(),
rs1 + Inst.ImmSignExt(12),
reinterpret_cast<std::make_unsigned_t<T>*>(&R->RV64[Inst.rd]),
req,
flags);
R->SetX(Inst.rd, static_cast<T>(R->RV64[Inst.rd]));
//std::cout << "RMT: Load Issued for address: " << std::hex << req.Addr << " Data: " << static_cast<T>(R->RV64[Inst.rd]) << std::dec << " Dest Reg: " << req.DestReg << std::endl;
//std::cout << "RMT: Load Issued for address: " << std::hex << req.Addr << " Data: " << static_cast<T>(R->RV64[Inst.rd]) << std::dec << " Dest Reg: " << req.DestReg << std::endl;
}

// update the cost
Expand All @@ -118,7 +118,7 @@ bool store(RevFeature *F, RevRegFile *R, RevMem *M, RevInst Inst) {
R->GetX<uint64_t>(Inst.rs1) + Inst.ImmSignExt(12),
R->GetX<T>(Inst.rs2));
R->AdvancePC(Inst);
// std::cout << "RMT: Store Issued for address: " << std::hex << R->GetX<uint64_t>(Inst.rs1) + Inst.ImmSignExt(12) << " Data: " << R->GetX<T>(Inst.rs2) << std::dec << std::endl;
// std::cout << "RMT: Store Issued for address: " << std::hex << R->GetX<uint64_t>(Inst.rs1) + Inst.ImmSignExt(12) << " Data: " << R->GetX<T>(Inst.rs2) << std::dec << std::endl;
return true;
}

Expand Down
5 changes: 0 additions & 5 deletions include/RevRegFile.h
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Expand Up @@ -176,11 +176,6 @@ class RevRegFile {
/// Set the current tracer
void SetTracer(RevTracer *t) { Tracer = t; }

/// Insert an item in the Load/Store Queue
void LSQueueInsert(std::pair<uint64_t, MemReq> item){
LSQueue->insert(std::move(item));
}

/// Get the MarkLoadComplete function
const std::function<void(const MemReq&)>& GetMarkLoadComplete() const {
return MarkLoadCompleteFunc;
Expand Down
22 changes: 9 additions & 13 deletions src/RevProc.cc
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Expand Up @@ -455,15 +455,15 @@ RevInst RevProc::DecodeCIInst(uint16_t Inst, unsigned Entry) const {
CompInst.imm = ((Inst & 0b1100000) >> 2); // [4:3]
CompInst.imm |= ((Inst & 0b1000000000000) >> 7); // [5]
CompInst.imm |= ((Inst & 0b11100) << 4); // [8:6]
CompInst.rs1 = 2; // Force rs1 to be x2 (stack pointer)
CompInst.rs1 = 2; // Force rs1 to be x2 (stack pointer)
}else if( (CompInst.opcode == 0b10) &&
(CompInst.funct3 == 0b010) ){
// c.lwsp
CompInst.imm = 0;
CompInst.imm = ((Inst & 0b1110000) >> 2); // [4:2]
CompInst.imm |= ((Inst & 0b1000000000000) >> 7); // [5]
CompInst.imm |= ((Inst & 1100) << 4); // [7:6]
CompInst.rs1 = 2; // Force rs1 to be x2 (stack pointer)
CompInst.rs1 = 2; // Force rs1 to be x2 (stack pointer)
}else if( (CompInst.opcode == 0b10) &&
(CompInst.funct3 == 0b011) ){
CompInst.imm = 0;
Expand All @@ -472,13 +472,13 @@ RevInst RevProc::DecodeCIInst(uint16_t Inst, unsigned Entry) const {
CompInst.imm = ((Inst & 0b1100000) >> 2); // [4:3]
CompInst.imm |= ((Inst & 0b1000000000000) >> 7); // [5]
CompInst.imm |= ((Inst & 0b11100) << 4); // [8:6]
CompInst.rs1 = 2; // Force rs1 to be x2 (stack pointer)
CompInst.rs1 = 2; // Force rs1 to be x2 (stack pointer)
}else{
// c.flwsp
CompInst.imm = ((Inst & 0b1110000) >> 2); // [4:2]
CompInst.imm |= ((Inst & 0b1000000000000) >> 7); // [5]
CompInst.imm |= ((Inst & 1100) << 4); // [7:6]
CompInst.rs1 = 2; // Force rs1 to be x2 (stack pointer)
CompInst.rs1 = 2; // Force rs1 to be x2 (stack pointer)
}
}else if( (CompInst.opcode == 0b01) &&
(CompInst.funct3 == 0b011) &&
Expand All @@ -491,7 +491,7 @@ RevInst RevProc::DecodeCIInst(uint16_t Inst, unsigned Entry) const {
CompInst.imm |= ((Inst & 0b100000) << 1); // bit 6
CompInst.imm |= ((Inst & 0b11000) << 4); // bit 8:7
CompInst.imm |= ((Inst & 0b1000000000000) >> 3); // bit 9
CompInst.rs1 = 2; // Force rs1 to be x2 (stack pointer)
CompInst.rs1 = 2; // Force rs1 to be x2 (stack pointer)
if( (CompInst.imm & 0b1000000000) > 0 ){
// sign extend
CompInst.imm |= 0b11111111111111111111111000000000;
Expand Down Expand Up @@ -557,7 +557,7 @@ RevInst RevProc::DecodeCSSInst(uint16_t Inst, unsigned Entry) const {
// c.fsdsp
CompInst.imm = 0;
CompInst.imm = ((Inst & 0b1110000000000) >> 7); // [5:3]
CompInst.imm |= ((Inst & 0b1110000000) >> 1); // [8:6]
CompInst.imm |= ((Inst & 0b1110000000) >> 1); // [8:6]
CompInst.rs1 = 2; // Force rs1 to x2 (stack pointer)
}else if( CompInst.funct3 == 0b110 ){
// c.swsp
Expand Down Expand Up @@ -642,7 +642,7 @@ RevInst RevProc::DecodeCLInst(uint16_t Inst, unsigned Entry) const {
// registers
CompInst.rd = ((Inst & 0b11100) >> 2);
CompInst.rs1 = ((Inst & 0b1110000000) >> 7);

//Apply compressed offset
CompInst.rd = CRegIdx(CompInst.rd);
CompInst.rs1 = CRegIdx(CompInst.rs1);
Expand Down Expand Up @@ -757,11 +757,8 @@ RevInst RevProc::DecodeCAInst(uint16_t Inst, unsigned Entry) const {

//Adjust registers for compressed offset
CompInst.rs2 = CRegIdx(CompInst.rs2);
CompInst.rs1 = CRegIdx(CompInst.rs1);
CompInst.rd = CRegIdx(CompInst.rd);

//All instructions of this format expand to <opcode> rd rd rs2, so set rs1 to rd
CompInst.rs1 = CompInst.rd;
CompInst.rs1 = CompInst.rd = CRegIdx(CompInst.rd);

CompInst.instSize = 2;
CompInst.compressed = true;
Expand Down Expand Up @@ -812,7 +809,7 @@ RevInst RevProc::DecodeCBInst(uint16_t Inst, unsigned Entry) const {
tmp[7] = o[7];
} else if( (CompInst.opcode == 0b01) && (CompInst.funct3 == 0b100)) {
//We have a shift or a andi
CompInst.rd = CompInst.rs1; //Already has compressed offset applied
CompInst.rd = CompInst.rs1; //Already has compressed offset applied
}

CompInst.offset = ((uint16_t)tmp.to_ulong()) << 1; // scale to corrrect position to be consistent with other compressed ops
Expand Down Expand Up @@ -1938,7 +1935,6 @@ bool RevProc::ClockTick( SST::Cycle_t currentCycle ){
AddThreadsThatChangedState(std::move(ActiveThread));
}
}

return rtn;
}

Expand Down