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1. Router_1x3_verification Router_1x3_verification Public

   Router 1x3 has single input port and three output ports.

   SystemVerilog 1

2. Driver-Drowsiness-detection Driver-Drowsiness-detection Public

   Python

3. UART-IP-CORE16550A-Verification-UVM UART-IP-CORE16550A-Verification-UVM Public

   The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a modem or other external devices, like another computer using…

   Verilog 17 2

4. async_fifo_uvm async_fifo_uvm Public template

   SystemVerilog 4 1

5. monsters-rolodex monsters-rolodex Public

   JavaScript

6. RISCV-RV32I RISCV-RV32I Public

   RISC-V RV32I Verilog Implementation