5 stage pipelined MIPS processor simulation with C++
The lab is a simulation of a pipelined MIPS processor with C++. The code simulates basic pipelined processor components including Memory, Registers, ALU, and output mechanism. It supports dependency-resolving techniques such as stalling, forwarding. This simulation is five-staged: Instruction Fetching (IF), Instructions Decode (ID), Execution (EX), Memory (MEM), Write Back (WB).