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13 public repositories
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Schematic, Layout Design & Simulation in 180nm Technology
This repository presents design of on-chip clock multiplier(8X PLL) using open source EDA tool OSU 180nm technology node
SRAM build space for the GF180MCU provided by GlobalFoundries.
Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.
Index of the fully open source process design kits (PDKs) maintained by Google.
7 track standard cells for GF180MCU provided by GlobalFoundries.
Updated
Dec 1, 2022
Verilog
IO and periphery cells for the GF180MCU provided by GlobalFoundries.
Updated
Dec 3, 2022
Verilog
9 track standard cells for GF180MCU provided by GlobalFoundries.
Updated
Dec 5, 2022
Verilog
SRAM macros created for the GF180MCU provided by GlobalFoundries.
Updated
Apr 10, 2023
Verilog
Digital standard cells for GF180MCU provided by Oklahoma State University.
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
Updated
May 31, 2023
Makefile
Primitives for GF180MCU provided by GlobalFoundries.
Updated
Aug 28, 2023
Python
Digital cell library designed in Magic for the TSMC 180nm process, with an accompanying data book generator script
Updated
Jan 31, 2024
Python
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