32-bit
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Microprocessor without Interlocked Pipelined Stages (MIPS) architectures
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May 19, 2019 - VHDL
Dieses Repository enthält die Implementierung eines RISC Prozessors mit VHDL, welche im Rahmen eines Projekts an der Universität Hamburg entstanden ist.
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Jan 24, 2023 - VHDL
Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python
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Apr 26, 2021 - VHDL
EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and imp…
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Jul 19, 2021 - VHDL
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