Microprocessor without Interlocked Pipelined Stages (MIPS) architectures
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Updated
May 19, 2019 - VHDL
Microprocessor without Interlocked Pipelined Stages (MIPS) architectures
Dieses Repository enthält die Implementierung eines RISC Prozessors mit VHDL, welche im Rahmen eines Projekts an der Universität Hamburg entstanden ist.
EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and imp…
Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python
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