ben-eater
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This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
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Nov 30, 2022 - Verilog
A FPGA implementation of Ben Eater's SAP-1 computer using the Digilent's BASYS 3 board.
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Jun 25, 2024 - Verilog
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