An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) of UM-SJTU JI.
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Updated
Dec 28, 2020 - Verilog
An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) of UM-SJTU JI.
MIPS single cycle Verilog implementation based on Computer Organization and Design The Hardware software Interface by David A. Patterson and John L. Hennessy.
contains my assignment submissions of EE2003 course in 2020
HDL Bits solution
MIPS CPU implemented in Verilog
21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 single cycle processor. 2.RISC-V64 five-stage pipelined processor. -Project3: Virtual memory, TLB, cache, memory simulator. -Project4: Literature review on Computer Organization.
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