digital-electronics
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4 bit up down counter counts from 0000 to 1111 if control input is set HIGH ,else it would count from 1111 to 0000. it can be build by cascading 4 nos of D flipflops with a mux at the input node to choose between UP/DOWN
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Jul 25, 2021 - Verilog
Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift re…
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Jul 25, 2021 - Verilog
Testing methodologies on circuits for reliability
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Jul 7, 2021 - Verilog
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the next. In this case, we can access the outputs of each D flip-flop in parallel. So, we will get parallel outputs …
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Jul 25, 2021 - Verilog
In this type of register, there are no interconnections between the individual flip-flops since no serial shifting of the data is required. Data is given as input separately for each flip flop and in the same way, output also collected individually from each flip flop.
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Jul 25, 2021 - Verilog
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Jul 19, 2022 - Verilog
Laboratory files for Integrated System Architectures course at Polito.
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Dec 19, 2021 - Verilog
METU EE314 Digital Electronics Laboratory Verilog Design Term Project
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Feb 18, 2023 - Verilog
THIS REPOSITORY CONTAINS DESIGN FILES FOR SPI TO 32 DIGITAL IO EXPANSION MODULE
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Nov 6, 2021 - Verilog
This is a repository containing solutions to the problem statements given in HDL Bits website.
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Jul 14, 2023 - Verilog
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we can receive the bits serially from the output of right most D flip-flop. Hence, this output is also…
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Jul 25, 2021 - Verilog
In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we will get the serial output from the right most D flip-flop.
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Jul 25, 2021 - Verilog
Source of USTC Digital Electromics Course ( Advanced Class).
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Aug 23, 2022 - Verilog
🖱️ "Digital Electronics Repo: A collection of digital circuits and simulations developed during the Digital Design Lab, organized for effective learning."
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Jun 29, 2024 - Verilog
Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT
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Jul 11, 2021 - Verilog
This repository contains codes of Verilog which is a Hardware Definition Language. These code can be easily compiled and simulate with a software called ModelSim.
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Dec 8, 2021 - Verilog
哈工大《数字电子技术基础》+《数字电子技术基础实验》
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May 26, 2018 - Verilog
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