FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
-
Updated
Jun 17, 2022 - SystemVerilog
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.
This repository contains different modules which execute arithmetic operations.
IP Module For LTC2311 ADC
Repository containing the code for implementing the classic game Pong on a Nexys A7 Digilent FPGA development board.
Add a description, image, and links to the digitaldesign topic page so that developers can more easily learn about it.
To associate your repository with the digitaldesign topic, visit your repo's landing page and select "manage topics."