#
fir
Here are 4 public repositories matching this topic...
The Design and Implementation of a Pulse Compression Filter on an FPGA.
fpga
matlab
fir
hilbert-transform
matched-filter
pulse-compression-filter
alpha-max-plus-beta-min
complex-fir
non-resoting-sqare-root
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Updated
Aug 7, 2021 - Verilog
Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual files. Download the project and run the main project file.
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Updated
Aug 25, 2019 - Verilog
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