Just a random compilation of some VHDL code
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Updated
Aug 9, 2023 - VHDL
Just a random compilation of some VHDL code
Modeling, Design and ASIC implementation of a tenth order FIR filter. This project has been developed in two versions: a basic one, and an improved one using 3-level unfolding and five stages pipeline.
ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
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