Super scalar Processor design
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Updated
Sep 7, 2014 - Verilog
Super scalar Processor design
A lite version of ARM CPU that extends ARM LEGv8
Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.
ARM Processor, Computer Architecture laboratory, University of Tehran
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