A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
-
Updated
May 20, 2022 - Verilog
A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
Verilog Implementation of an ARM LEGv8 CPU
Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.
ARM Processor, Computer Architecture laboratory, University of Tehran
An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) of UM-SJTU JI.
Verilog Implementation of an ARM LEGv8 CPU
A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.
Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor
Add a description, image, and links to the hazard-detection topic page so that developers can more easily learn about it.
To associate your repository with the hazard-detection topic, visit your repo's landing page and select "manage topics."