5 stages RISC pipelined processor with multiple instructions implemented in verilog including ALU Operations, Interrupts as a state machine, Jumps and branching instructions, Memory operations and more.. following Harvard architecture.
memory
assembler
verilog
systemverilog
computer-architecture
interrupts
hazards
pipelined-processors
alu-digital-circuit
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Updated
Jan 7, 2023 - SystemVerilog