This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.
Parallel Prefix Adders achieve logarithmic time complexity by means of parallelizing the operation. For an n bit prefix adder, the critical path is one xor gate, one and/or gate and log(n) modules.
Add a description, image, and links to the parallel-prefixsum topic page so that developers can more easily learn about it.
To associate your repository with the parallel-prefixsum topic, visit your repo's landing page and select "manage topics."