risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 30 public repositories matching this topic...
-
Updated
Jun 6, 2021 - Shell
Docker containers with support for RISC-V
-
Updated
Mar 12, 2024 - Shell
⛔ DEPRECATED ⛔ HERO toolchain with support for RISC-V offloading over OpenMP Accelerator Execution Model
-
Updated
Jan 6, 2022 - Shell
Ubuntu Core OS Build Framwork
-
Updated
Mar 11, 2024 - Shell
my progress and contribution yocto project in tessolve
-
Updated
Apr 28, 2023 - Shell
stock ubuntu riscv64 linux for the starfive visionfive v2
-
Updated
Dec 24, 2023 - Shell
Make a Debian image for some RISC-V boards
-
Updated
Apr 24, 2023 - Shell
Build openSUSE images for the Allwinner D1
-
Updated
Aug 23, 2023 - Shell
Community-maintained SVD description of the BL602 SoC.
-
Updated
Feb 9, 2021 - Shell
Emulating other CPU architectures in Docker made easy
-
Updated
Mar 9, 2022 - Shell