RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 170 public repositories matching this topic...
HiFive01-RevB is the SiFive's RISC-V based board
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Nov 14, 2023 - C
A pipelined version of my previous single-cycle implementation of the RISCV ISA
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Aug 20, 2021 - C
My parsec-benchmark development fork, with some tweaks.
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Feb 13, 2021 - C
Fork to add RISC-V specific GCC built-in functions and machine descriptions for extended instructions for ASCON cryptography algorithm.
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Apr 23, 2021 - C
Strassen and Winograd algorithms for efficient matrix multiplication
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May 6, 2020 - C
Nuclei RISC-V Simple Segger Embedded Studio Projects
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Jun 8, 2023 - C