HLSM with memory design for max pooling algorithm.
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Updated
Jan 18, 2021 - VHDL
HLSM with memory design for max pooling algorithm.
Final project: Tic-tac-toe on VGA monitor. ENGS31/CS56 Digital Electronics @ Dartmouth.
Simple RTL model for Interger Numbers Calculation using RAM and 7 Segment Display.
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