A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
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Updated
Jun 13, 2024 - SystemVerilog
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
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