RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100
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Jul 11, 2024 - VHDL
RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100
A 5-stage pipeline CPU of RISC-V ISA. Guided by SUSTech CS214 Computer Organization(H)
2023 Fall CS207 Digital Design Course Project with 120/100 (Full Score)
SUSTech CS Course related files (lecture notes, assignments, review notes, etc)
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