System-Verilog implementation of the ACDMA crossbar
-
Updated
Nov 25, 2018 - SystemVerilog
System-Verilog implementation of the ACDMA crossbar
All projects that utilize the Verilog & SystemVerilog HDL's.
Attempt at building entirely from scratch a RISC-V SoC for self-education purposes.
RISC-V SoC
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
🌌 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.
Add a description, image, and links to the system-on-chip topic page so that developers can more easily learn about it.
To associate your repository with the system-on-chip topic, visit your repo's landing page and select "manage topics."