A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
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Updated
Jul 3, 2024 - SystemVerilog
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
All projects that utilize the Verilog & SystemVerilog HDL's.
🌌 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.
Attempt at building entirely from scratch a RISC-V SoC for self-education purposes.
RISC-V SoC
System-Verilog implementation of the ACDMA crossbar
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