Simplified implementation of MIPS pipelined processor
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Updated
May 8, 2018 - VHDL
Simplified implementation of MIPS pipelined processor
TLC designed vhdl which changes the green light time depending on the traffic in that specfic lane
This is a simulation based VHDL code developed in Xilinx to demonstrate a 4-bit PN sequence generator.
VHDL Code for Labs done in a 2nd year Digital Systems course at Queen's University.
A simple sram controller and test for the altera DE1 FPGA board
Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board
FPGA design project for the course "Reti Logiche" of Politecnico di Milano, a.y. 2018/2019
This repository contains beginner to intermediate level of codes for VHDL and Basys 3.
Programmable Systems Design Course Teaching Assistant at Tehran Polytechnic
Direct digital frequency synthesizer in Verilog and VHDL.
EGR 480 - Digital Integrated Circuit Design and FPGAs
Programmable Digital Systems Design Course Materials
This repository contains VHDL files of different Digital Designs.
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