Design rule checker for VLSI layouts
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Updated
Jun 21, 2024 - C++
Design rule checker for VLSI layouts
Coursework of NTHU CS512200 VLSI Design for Manufacturability
Coursework of NTHU CS613500 VLSI Physical Design Automation
digital and analog cosimulation for ACT and Xyce
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers on FPGAs
A collection of Schematics, PCBs and VLSI work on various platforms
Template project for using gatery
A customized placer based on the RePlAce global placement tool.
SystemC Open Source Implementation Clone from Accellera.org
This repository include some of the most fundamental concepts of VLSI design automation
Accelerated Stencil Computation with Optimized Dataflow Architecture on FPGAs
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
demo on simple channel router
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