Simple Ping Pong game on Xilinx Spartan 3E
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Updated
Apr 29, 2022 - HTML
Simple Ping Pong game on Xilinx Spartan 3E
It is a simplified GPIO interrupt example for Xilinx ZYNQ FPGA.
This repository contains lab assignments done in the course CS220: Computer Organization at IIT Kanpur
Just running through some verilog examples
4bit_CLA_Adder_7seg in Xilinx Vivado Verilog
CS M152B Codebase Fall 2018
Verilog for a Field Programmable Gate Array Engineer with Xilinx Vivado Design Suite.
A VHDL Project using ISE 14.7, developed on a Xilinx Spartan 6
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