Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
-
Updated
May 2, 2019 - C++
Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
Custom IP for the Mini-EUSO PDM-DP Zynq system
Add a description, image, and links to the xilinx-hls topic page so that developers can more easily learn about it.
To associate your repository with the xilinx-hls topic, visit your repo's landing page and select "manage topics."