Revert "drm/vc4: Correct interrupt enable bits on hvs4"

BugLink: https://bugs.launchpad.net/bugs/1964144

This reverts commit fae5987.

(cherry picked from commit 1db761647f65dd032d4f3921bf91f9ff3ff8e76e rpi-5.15.y)
Signed-off-by: Juerg Haefliger <juergh@canonical.com>

Author: mripard

drivers/gpu/drm/vc4/vc4_hvs.c

@@ -644,7 +644,7 @@ static void vc4_hvs_install_dlist(struct vc4_dev *vc4, unsigned int channel)
 	hvs->fifo[channel].pending = false;
 
 	reg = HVS_READ(SCALER_DISPCTRL);
-	reg &= ~BIT(7 + (channel * (vc4->hvs->hvs5 ? 4 : 2)));
+	reg &= ~BIT(7 + (channel * 4));
 	HVS_WRITE(SCALER_DISPCTRL, reg);
 
 	spin_unlock_irqrestore(&hvs->hw_dlist_lock, flags);
@@ -664,7 +664,7 @@ static void vc4_hvs_schedule_dlist_update(struct vc4_dev *vc4,
 	}
 
 	HVS_WRITE(SCALER_DISPCTRL,
-		  HVS_READ(SCALER_DISPCTRL) | BIT(7 + (channel * (vc4->hvs->hvs5 ? 4 : 2))));
+		  HVS_READ(SCALER_DISPCTRL) | BIT(7 + (channel * 4)));
 
 	hvs->fifo[channel].pending = true;