drm/vc4: crtc: Support odd horizontal timings on BCM2712

BCM2711 runs pixelvalve at two pixels per clock cycle which results
in an unfortunate limitation that odd horizontal timings are not
possible. This is apparent on the standard DMT mode of 1366x768@60
which cannot be driven with correct timing.

BCM2712 defaults to the same behaviour, but has a mode to support
odd timings. While internally it still runs at two pixels per clock,
setting the PV_VCONTROL_ODD_TIMING bit makes it appear externally
to behave as it is one pixel per clock.

Switching to this mode fixes 1366x768@60 mode, and other custom
resultions with odd horizontal timings.

Signed-off-by: Dom Cobley <popcornmix@gmail.com>
(cherry picked from commit 06e5f82e61aca21050d66887b44fd7e3bff13591 rpi-6.6.y)
Signed-off-by: Juerg Haefliger <juerg.haefliger@canonical.com>

Author: popcornmix

drivers/gpu/drm/vc4/vc4_crtc.c

@@ -399,12 +399,6 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
 
 	vc4_crtc_pixelvalve_reset(crtc);
 
-	/*
-	 * NOTE: The BCM2712 has a H_OTE (Horizontal Odd Timing Enable)
-	 * bit that, when set, will allow to specify the timings in
-	 * pixels instead of cycles, thus allowing to specify odd
-	 * timings.
-	 */
 	CRTC_WRITE(PV_HORZA,
 		   VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
 				 PV_HORZA_HBP) |
@@ -449,6 +443,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
 		 */
 		CRTC_WRITE(PV_V_CONTROL,
 			   PV_VCONTROL_CONTINUOUS |
+			   (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
 			   (is_dsi ? PV_VCONTROL_DSI : 0) |
 			   PV_VCONTROL_INTERLACE |
 			   (odd_field_first
@@ -460,6 +455,7 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
 	} else {
 		CRTC_WRITE(PV_V_CONTROL,
 			   PV_VCONTROL_CONTINUOUS |
+			   (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
 			   (is_dsi ? PV_VCONTROL_DSI : 0));
 		CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 	}
@@ -1332,7 +1328,7 @@ const struct vc4_pv_data bcm2712_pv0_data = {
 		.hvs_output = 0,
 	},
 	.fifo_depth = 64,
-	.pixels_per_clock = 2,
+	.pixels_per_clock = 1,
 	.encoder_types = {
 		[0] = VC4_ENCODER_TYPE_HDMI0,
 	},
@@ -1345,7 +1341,7 @@ const struct vc4_pv_data bcm2712_pv1_data = {
 		.hvs_output = 1,
 	},
 	.fifo_depth = 64,
-	.pixels_per_clock = 2,
+	.pixels_per_clock = 1,
 	.encoder_types = {
 		[0] = VC4_ENCODER_TYPE_HDMI1,
 	},

drivers/gpu/drm/vc4/vc4_hdmi.c

@@ -3917,7 +3917,7 @@ static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = {
 		PHY_LANE_2,
 		PHY_LANE_CK,
 	},
-	.unsupported_odd_h_timings	= true,
+	.unsupported_odd_h_timings	= false,
 	.external_irq_controller	= true,
 
 	.init_resources		= vc5_hdmi_init_resources,
@@ -3944,7 +3944,7 @@ static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = {
 		PHY_LANE_2,
 		PHY_LANE_CK,
 	},
-	.unsupported_odd_h_timings	= true,
+	.unsupported_odd_h_timings	= false,
 	.external_irq_controller	= true,
 
 	.init_resources		= vc5_hdmi_init_resources,

drivers/gpu/drm/vc4/vc4_regs.h

@@ -155,6 +155,7 @@
 # define PV_CONTROL_EN				BIT(0)
 
 #define PV_V_CONTROL				0x04
+# define PV_VCONTROL_ODD_TIMING			BIT(29)
 # define PV_VCONTROL_ODD_DELAY_MASK		VC4_MASK(22, 6)
 # define PV_VCONTROL_ODD_DELAY_SHIFT		6
 # define PV_VCONTROL_ODD_FIRST			BIT(5)