GTOS: Testing Blueprint

Tier 1 and Tier 2 Harness Testing

Shared Requirements

To maintain a unified architecture across the entire system, both Tier 1 and Tier 2 test suites must fulfill these shared foundational mandates:

• Dual-Target Lifecycle: Every harness must serve a dual purpose, acting as a development-side validation check today and compiling into a permanent, bare-metal utility tool tomorrow.
• Uncompiled Host Accessibility: Developers must be able to invoke the harnesses on a local development machine (Mac/Linux) prior to target deployment to inspect code health and verify pipeline states.
• Native Silicon Compilation: Every script must be 100% physically capable of compiling down to pure, unallocated machine code targeting native silicon.
• GT-OS Shell Integration: Upon deployment, all harnesses merge directly into the core platform to form the native system monitor utility suite accessible via the shell.
• Anti-Drift Double-Blind Sheets: Every testing suite must evaluate live state parameters to output a deterministic cryptographic fingerprint alongside scrambled decoy options.
• Zero Core-Code Impact: Testing mechanisms must read, stress-test, and execute block logic without altering or adding boilerplate to the core operating system files.

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Tier 1 Harness Testing (Layers 1–4 Unique)

1. Architectural Scope

Tier 1 harnesses act as isolated, targeted simulations of single physical layers. They operate outside the unified system library crate, reaching directly into specific, raw source directories via relative compilation directives.

2. Execution & Command Environment

• Dual-Engine Support: Natively compatible with both raw rustc and cargo host orchestration routes.
• Host Execution: Compiles effortlessly directly on a local desktop machine environment (Mac/Linux).
• System Library Coupling: Fully independent. They require zero upstream workspace dependency building or pre-compiled object file binding.

3. Display & Validation Vectors

• Output Path: Relies on standard host system macros to stream data straight to the terminal workspace monitor.
• Metrics Tracked: Validates static register memory layouts, packed fixed-point matrix dimensions, and localized safety containment checks (e.g., 11-byte hardware constraints or emergency brake traps).
• Anti-Drift Verification: Generates a clean, local mathematical state fingerprint alongside a shuffled, clock-scrambled option block (Options A, B, and C). This text sheet provides the double-blind answer key needed to confirm matching compiler profiles.

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Tier 2 Harness Testing (Conductor & Layer 5+ Unique)

1. Architectural Scope

Tier 2 harnesses act as integrated ecosystem monitors. They validate the master orchestration loops and peripheral instrument frameworks. Because they test cross-tier coordination, they are deeply coupled to the complete, unified operating system library crate.

2. Execution & Command Environment

• Target Target Isolation: Designed to run cleanly inside virtual execution containers (like QEMU) or directly on bare-metal hardware.
• Host-Side Linking Boundaries: When triggered on a standard desktop machine (Mac/Linux), the compiler encounters hard symbol collisions (such as duplicate panic implementations) because a strict bare-metal environment lacks the dynamic linking models required by host operating system layers.
• System Library Coupling: Completely integrated. They require a fully evaluated compilation of the monolithic system tree before execution can begin.

3. Display & Validation Vectors

• Output Path: Bypasses heavy desktop terminal macros entirely. For production and on-silicon testing, outputs are routed through unallocated, bare-metal writing mechanisms targeting physical hardware registers (such as VGA text-mode boundaries).
• Metrics Tracked: Focuses entirely on end-to-end interconnectivity, live master clock cycle increments, and multi-layer pipeline scheduling synchronization (ensuring system chords execute without latency, drops, or memory leaks).
• Introspective Code Signals: Uses the compiler's native dead-code or unused-parameter analysis blocks as active operational signals. The presence of these specific compilation warnings verifies that the harness has successfully threaded its routes through the entire underlying core state layout.