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Implementation of the circular convolution of two arrays with fixed point real numbers using the SystemVerilog HDL

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Circular Convolution Module

SystemVerilog synthesizable module that implements circular convolution buffer.

  • Verification is done using Cocotb and Icarus Verilog.
  • Formal verification is done with SymbiYosys
  • Synthesis is done via Quartus Prime for DE10-Lite board and via OpenLane for Skywater130nm

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Implementation of the circular convolution of two arrays with fixed point real numbers using the SystemVerilog HDL

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