Support modules which are never used with their default parameter values

[veripoolbot]

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Author Name: Alex Solomatnikov
Original Redmine Issue: 470 from https://www.veripool.org
Original Date: 2012-03-24
Original Assignee: Wilson Snyder (@wsnyder)

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Code:

module test_inst (
         clk,
         reset_n,
         dout
);

         parameter MEM_DQ_WIDTH                          = "";
         parameter MEM_READ_DQS_WIDTH                    = "";

         localparam NUMBER_OF_READ_DQ_PER_DQS = MEM_DQ_WIDTH / MEM_READ_DQS_WIDTH;
         
         input clk;
         input reset_n;
         output  dout;

         wire [NUMBER_OF_READ_DQ_PER_DQS - 1:0] error_word;

         wire [NUMBER_OF_READ_DQ_PER_DQS - 1:0] processed_error_word;
         
         genvar rank;
         generate
                 for(rank = 0; rank < NUMBER_OF_READ_DQ_PER_DQS; rank = rank + 1)
                 begin: error_word_gen
                         assign processed_error_word[rank] = (error_word[rank] !== 1'b0);
                 end
         endgenerate

endmodule


module test (
                 input  wire         clk,
                 input  wire         reset
         );

         test_inst #(
                 .MEM_DQ_WIDTH                         (72),
                 .MEM_READ_DQS_WIDTH                   (9)
                ) u_test_inst (
                 .clk           (clk),
                 .reset_n       (~reset),
                 .dout          ()
         );

endmodule

error:

verilator -sp -Wno-fatal --top-module test test.v
%Warning-WIDTH: test.v:22: Operator LT expects 32 bits on the RHS, but RHS's VARREF 'NUMBER_OF_READ_DQ_PER_DQS' generates 1 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: test.v:22: Unsupported: Can't unroll generate for; init/final/increment too large or four state
%Error: test.v:22: For loop doesn't have genvar index, or is malformed
%Error: test.v:22: Unsupported: Can't unroll generate for; init/final/increment too large or four state
%Error: test.v:22: For loop doesn't have genvar index, or is malformed
%Error: Exiting due to 4 error(s)
%Error: Command Failed /tools/verilator/verilator-3.832/bin/verilator_bin -sp -Wno-fatal --top-module test test.v

VCS compiles this code without complaints.

[veripoolbot]

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-03-24T01:21:38Z

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If I change code to:

         parameter MEM_DQ_WIDTH                          = 0;
         parameter MEM_READ_DQS_WIDTH                    = 0;

it still does not compile.

However, if I change it to:

         parameter MEM_DQ_WIDTH                          = 1;
         parameter MEM_READ_DQS_WIDTH                    = 1;

verilator compiles it.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-24T14:19:58Z

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This is because there is a division by 0 in the module before parameter expansion. At present Verilator needs "all-defaulted" pararameter version of a module to be legal; at a later stage it will realize it is never used and remove it. This will need to be fixed, which unfortunately is not a quick fix.

[veripoolbot]

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-03-24T15:49:24Z

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Unfortunately, this is really common in the IP code I am trying to compile with verilator, so it is not easy to hack around, unlike #� and others. In fact, I was completely stalled yesterday after trying to for several hours to modify the code - there are just too many cases of parameters with default values equal to "".

One more thing to note here is that it looks like there is also always a width warning in such cases:

%Warning-WIDTH: test.v:22: Operator LT expects 32 bits on the RHS, but RHS's VARREF 'NUMBER_OF_READ_DQ_PER_DQS' generates 1 bits.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-24T19:56:01Z

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It occurred to me that I could just not do parameter expansion on modules that aren't used and leave the eliminating of them as it is now.

Fixed in git towards 3.833.

[veripoolbot]

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Original Redmine Comment
Author Name: Alex Solomatnikov
Original Date: 2012-03-25T00:29:06Z

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Thanks for the fix! This was the last issue in the IP block, although I still have to try to compile all the libraries.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-04-15T20:39:11Z

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In 3.833.