- Top module:
tt_um_william_pll - Language: Verilog
- Target shuttle: SKY26a (
sky130A, digital tile) - Project docs: docs/info.md
- William Anthony
- Electrical Engineering, Bandung Institute of Technology (ITB)
- Built in 6th semester (admitted in 2023)
- LinkedIn: https://www.linkedin.com/in/wlmoi/
- GitHub: https://github.com/wlmoi
- Instagram: https://www.instagram.com/wlmoi/
Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.
To learn more and get started, visit https://tinytapeout.com.
This design wraps a smartcard-oriented PLL model into the Tiny Tapeout user module interface.
The reference input uses Tiny Tapeout clk, and the PLL is intentionally controlled by an explicit enable bit.
enamust be high (project selected)rst_nmust be high (reset released)ui[0]must be set to1to enable PLL operation
When ui[0] is set back to 0, the PLL path is intentionally disabled and output clocks are expected to stop.
- Inputs (
ui_in)ui[0]: PLL enableui[7:4]: divider ratio config nibble
- Bidirectional (
uio)uio[3:0]input: charge pump gain configuio[7:4]output: VCO monitor bits
- Outputs (
uo_out)uo[0]: lockuo[1]: almost_lockuo[2]: clk_div4uo[3]: clk_div2uo[4]: pll_clk_outuo[5]: pfd_upuo[6]: pfd_downuo[7]: enable status
From test/ run:
make -BThe cocotb test verifies disabled state, enabled oscillation, and disabled-again behavior.
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