Computer Architecture

Hw1: Implementation of binary search tree in both C and Python. Observing 'performance differences' between these two different languages.

Hw2: Implementation of some binary search tree operations in MIPS assembly language.

Hw3: Implementing instructions in Verilog with MIPS-lite single-cycle datapath and revised control units.

Hw4: In this assignment, I've run a set of experiments and analysed the results in order to understand the cache behavior of programs, how different cache designs affect program execution.

(pdf documents that include detailed explanations can be found in the folders)