Update Xilinx QEMU repo to fix CANFD interrupt handling #2
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This removes the old module that has been unused since Xilinx BBRAM device accepted in upstream. Signed-off-by: Tong Ho <tong.ho@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
This removes, from hw/block, all Xilinx eFUSE related files, all of which have been replaced by upstream implementations in hw/nvram. Signed-off-by: Tong Ho <tong.ho@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Add reset related traces to the CRP models of the PMC and PMX sub-systems. Those traces are: - xlnx_versal_pmc_crp_power_on_reset - xlnx_versal_pmc_crp_soft_reset They are triggered on RST_PS writes and report the subsystem (PS, PL or PMC) for which the reset state is toggled. Those traces can help developers to catch reset events on the sub-systems. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
GIC proxy is a generic model used across different platforms. A few platforms have irqs connected in fields currently reserved. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Set atomic field in ID_AA64ISAR0_EL1 to 0b0010 to indicate support for FEAT_LSE (Large System Extensions) atomic instructions. This enables guests to detect atomic support via the standard aarch64 feature register for Cortex-A78. Signed-off-by: John Vicky Vykuntapu <johnvicky.vykuntapu@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Set ps sysmon startup_state status to Idle (PS SysMon is Ready), this will fix the xilinx-ams probe failed error. Signed-off-by: Shiva sagar Myana <Shivasagar.Myana@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
The decode error traces were logged using qemu_log(). Use qemu_log_mask() with LOG_GUEST_ERROR instead to avoid polluting stderr. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
With DCA counter-measures enabled, when the device send block, it alternates between a pseudo-random value block and the data block masked by this value. Until now the model was sending a block full of zeros as a mask. This can be an issue if the firmware checks the mask as the counter-measure become useless with a null mask. Change this to a constant non-null mask block, which should be enough for most use-cases. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Add a comment explaining what this GPI_ENABLE register is about for the next reader of the code. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Do not expose a GPI in the device register when it is masked (not enabled) in the PMU_LOCAL. Note that because of the GPI_ENABLE hack, this fix is done in this device model and not in the PMU_LOCAL one. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Split the TYPE_XLNX_ZDMA type into base and concrete classes. This is in preparation for the Versal Gen 2 version of the zdma. Signed-off-by: Shiva sagar Myana <Shivasagar.Myana@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
This is a non functional restructure of the xlnx-zdma model to be able to reuse the interrupt registers in an updated version of the model found on AMD's Versal Gen 2. Signed-off-by: Shiva sagar Myana <Shivasagar.Myana@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Add support for the ZDMA V2 model. Key updates from the V1 model include: * Introduction of error status registers. * Updated register offset of interrupt registers. Signed-off-by: Shiva sagar Myana <Shivasagar.Myana@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
If EU mode is enabled, the TRNG returns internal raw entropy values to the core_output instead of pseudo-random numbers, as the PRNG unit is disabled in this mode. Signed-off-by: Shiva sagar Myana <Shivasagar.Myana@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
TX_THRES and RX_THRES sized are according the corresponding hardware FIFO size configuration. Unimplemented MSBs are RAZ/WI. Drivers use this property to detect the FIFO size. Mask out the written value to ensure this. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
glibc 2.41+ has added [1] definitions for sched_setattr and sched_getattr functions and struct sched_attr. Therefore, it needs to be checked for here as well before defining sched_attr, to avoid a compilation failure. Define sched_attr conditionally only when SCHED_ATTR_SIZE_VER0 is not defined. [1] https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=21571ca0d70302909cf72707b2a7736cf12190a0;hp=298bc488fdc047da37482f4003023cb9adef78f8 Signed-off-by: Khem Raj <raj.khem@gmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2799 Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Calling memset on a local variable is awkward, and this particular call is unnecessary because the variable gets initialized after in all branches of the control flow. Drop the memset. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
i varies from 0 to 63. Fix the shift accordingly. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
xilinx_qspips_write puts a 1MiB buffer on the stack. This can easily triggers a stack overflow depending on the call stack. Fix that by allocating the buffer instead. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
The gpios sections of the default_gpio_sets array were missing the sentinels. Add them. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
The number of PHY registers is 32, from 0 to 31. Fix this. Signed-off-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
The interrupt level should be 0 or 1. The existing code was using the interrupt flags to determine the level. In the only machine currently supported (xlnx-versal-virt), the GICv3 was masking off all bits except bit 0 when applying it, resulting in the IRQ never being delivered. Signed-off-by: Doug Brown <doug@schmorgal.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Message-id: 20240827034927.66659-2-doug@schmorgal.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
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From zephyrproject-rtos/xilinx-qemu#2: > There are just couple of patches to be merged. All of them are going > to be the part of 2025.2 tag and the main reason is top commit which > is fixing interrupt level for CANFD core. With this new version CANFD > test can run on QEMU. > Also 3 patches to fix ZDMA behavior which affect DMA tests. > And enabling FEAT_LSE support for Cortex-a78 with autodetection. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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Opened a PR pulling this on the sdk-ng side for testing: zephyrproject-rtos/sdk-ng#1034 |
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From zephyrproject-rtos/xilinx-qemu#2: > There are just couple of patches to be merged. All of them are going > to be the part of 2025.2 tag and the main reason is top commit which > is fixing interrupt level for CANFD core. With this new version CANFD > test can run on QEMU. > Also 3 patches to fix ZDMA behavior which affect DMA tests. > And enabling FEAT_LSE support for Cortex-a78 with autodetection. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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From zephyrproject-rtos/xilinx-qemu#2: > There are just couple of patches to be merged. All of them are going > to be the part of 2025.2 tag and the main reason is top commit which > is fixing interrupt level for CANFD core. With this new version CANFD > test can run on QEMU. > Also 3 patches to fix ZDMA behavior which affect DMA tests. > And enabling FEAT_LSE support for Cortex-a78 with autodetection. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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There are just couple of patches to be merged. All of them are going to be the part of 2025.2 tag and the main reason is top commit which is fixing interrupt level for CANFD core. With this new version CANFD test can run on QEMU.
Also 3 patches to fix ZDMA behavior which affect DMA tests.
And enabling FEAT_LSE support for Cortex-a78 with autodetection.