drivers: sdmmc: stm32: introduce cache flush & invalidation for DMA

Introduce steps to maintain cache coherence around DMA accesses to the
underlying SD / eMMC storage.

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>

Author: attie-argentum

drivers/disk/sdmmc_stm32.c

@@ -17,6 +17,7 @@
 #include <zephyr/pm/policy.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
+#include <zephyr/cache.h>
 #include <soc.h>
 #include <stm32_ll_rcc.h>
 
@@ -518,6 +519,12 @@ static int stm32_sdmmc_read_blocks(HandleTypeDef *hsd, uint8_t *data_buf,
 
 #if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma))
 
+	/* A flush is performed before the DMA operation, to prevent accidental data
+	 * loss when the buffer is not properly aligned to the cache-line (e.g:
+	 * 32-bytes for STM32H7).
+	 */
+	sys_cache_data_flush_and_invd_range(data_buf, BLOCKSIZE * num_sector);
+
 #ifdef CONFIG_SDMMC_STM32_EMMC
 	hal_ret = HAL_MMC_ReadBlocks_DMA(hsd, data_buf, start_sector, num_sector);
 #else
@@ -568,6 +575,13 @@ static int stm32_sdmmc_access_read(struct disk_info *disk, uint8_t *data_buf,
 
 	k_sem_take(&priv->sync, K_FOREVER);
 
+#if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma))
+	/* Invalidate after the operation is complete, to protect against
+	 * speculative / spurious reads.
+	 */
+	sys_cache_data_invd_range(data_buf, BLOCKSIZE * num_sector);
+#endif
+
 #if STM32_SDMMC_USE_DMA_SHARED
 	if (HAL_DMA_DeInit(&priv->dma_txrx_handle) != HAL_OK) {
 		err = -EIO;
@@ -598,6 +612,8 @@ static int stm32_sdmmc_write_blocks(HandleTypeDef *hsd,
 
 #if STM32_SDMMC_USE_DMA || IS_ENABLED(DT_PROP(DT_DRV_INST(0), idma))
 
+	sys_cache_data_flush_range(data_buf, BLOCKSIZE * num_sector);
+
 #ifdef CONFIG_SDMMC_STM32_EMMC
 	hal_ret = HAL_MMC_WriteBlocks_DMA(hsd, data_buf, start_sector, num_sector);
 #else