drivers: rtc: stm32: It's not possible to set the time when device runtime pm is enabled and LSE is enabled.

[coran21]

Describe the bug
In order to set the time or any other RTC register, the backup domain protection has to be disabled by LL_PWR_EnableBkUpAccess.
Normally, this is called once during RTC initialization and everything works fine. After enabling device runtime PM and LSE, the set_up_fixed_clock_sources function is called every time after waking up by PM, and part of this function is enabling backup domain protection when LSE is active. This leads to the situation when backup domain protection is enabled all the time and setting the RTC time doesn't work.

Relevant code from function set_up_fixed_clock_sources in file clock_stm32_ll_common.c :

	if (IS_ENABLED(STM32_LSE_ENABLED)) {
		/* LSE belongs to the back-up domain, enable access.*/

		z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);

#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || defined(PWR_DBPR_DBP)
		/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
		LL_PWR_EnableBkUpAccess();
		while (!LL_PWR_IsEnabledBkUpAccess()) {
			/* Wait for Backup domain access */
		}
#endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPR_DBP */

#if STM32_LSE_DRIVING
		/* Configure driving capability */
		LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
#endif

		if (IS_ENABLED(STM32_LSE_BYPASS)) {
			/* Configure LSE bypass */
			LL_RCC_LSE_EnableBypass();
		}

		/* Enable LSE Oscillator (32.768 kHz) */
		LL_RCC_LSE_Enable();
		while (!LL_RCC_LSE_IsReady()) {
			/* Wait for LSE ready */
		}

#ifdef RCC_BDCR_LSESYSEN
		LL_RCC_LSE_EnablePropagation();
		/* Wait till LSESYS is ready */
		while (!LL_RCC_LSE_IsPropagationReady()) {
		}
#endif /* RCC_BDCR_LSESYSEN */

#if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || defined(PWR_DBPR_DBP)
		LL_PWR_DisableBkUpAccess();
#endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPR_DBP */

Please also mention any information which could help others to understand
the problem you're facing:

• What target platform are you using?
  STM32L4R5
• What have you tried to diagnose or workaround this issue?
  Disabling backup domain protection before setting RTC time fixes the problem

To Reproduce
Steps to reproduce the behavior:

1. enable RTC, device runtime PM, and LSE
2. set RTC time

Expected behavior
Time is set correctly

Impact
The code execution is halted due to a never-ending while loop in the RTC driver.

Environment (please complete the following information):

• OS: Linux
• Toolchain: Zephyr SDK

My suggested fix is to disable backup domain protection in rtc_stm32_set_time, I can prepare a PR.

[erwango]

My suggested fix is to disable backup domain protection in rtc_stm32_set_time, I can prepare a PR.

If you do so, please additionally fix drivers/rtc/rtc_ll_stm32.c.

Note:
I had a look to LL_PWR_EnableBkUpAccess()/LL_PWR_DisableBkUpAccess() calls and there is a more global issue on this:

• Disable Bckup access is not called in set_up_fixed_clock_sources in drivers/clock_control/clock_stm32_ll_h7.c. This has to be fixed for consistency across series.
• 2 drivers are implemented with the assumption that Back up Domain access is enabled:
  • drivers/bbram/bbram_stm32.c: Disable/Enable should be added around the write function. @semihalf-duda-patryk I'm surprised you've never faced any issue related to this point.
  • soc/arm/st_stm32/common/stm32_backup_sram.c: It is mapping backup RAM as a RAM region accessible to the system. I don't see other option than enabling access globally and never disabling access. This should be controlled by a Kconfig option and a STM32 API should be added to control access disabling.

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