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STM32MP1 Series support #13794
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38ac81a
soc: stm32: add initial soc support for stm32mp1 family
arnopo cfae159
ext: hal: Enable support for stm32mp1xx hal
arnopo 685c57d
ext: hal: add stm32mp1 exti ll driver
arnopo 3d2e8c0
dts: add declaration of stm32mp157
arnopo 5d2f4a5
drivers/interrupt_controller: stm32: add support of stm32mp1
arnopo 02d6cca
boards: arm: Add support for STM32MP157 Discovery board
arnopo ff16fac
ext: hal: fix naming in rcc ll
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| # Copyright (c) 2019 STMicroelectronics | ||
| # | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
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| zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers) |
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| # Kconfig - STM32MP157C Discovery board configuration | ||
| # | ||
| # Copyright (c) 2019 STMicroelectronics | ||
| # | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
| # | ||
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| config BOARD_STM32MP157C_DK2 | ||
| bool "STM32MP157C Discovery Development 2 Board" | ||
| depends on SOC_STM32MP15_M4 |
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| # Kconfig - STM32MP157 discovery board configuration | ||
| # | ||
| # Copyright (c) 2019 STMicroelectronics | ||
| # | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
| # | ||
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| if BOARD_STM32MP157C_DK2 | ||
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| config BOARD | ||
| default "stm32mp157c_dk2" | ||
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| endif # BOARD_STM32MP157_Dk2 |
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| include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) |
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| .. _stm32mp157c_dk2_board: | ||
|
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| ST STM32MP157C-DK2 Discovery | ||
| ############################ | ||
|
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| Overview | ||
| ******** | ||
|
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| The STM32MP157-DK2 Discovery board leverages the capacities of the STM32MP157 | ||
| multi-core processor,composed of a dual Cortex®-A7 and a single Cortex®-M4 core. | ||
| Zephyr OS is ported to run on the Cortex®-M4 core. | ||
|
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| - Common features: | ||
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| - STM32MP157: | ||
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| - Arm®-based dual Cortex®-A7 32 bits | ||
| - Cortex®-M4 32 bits | ||
| - embedded SRAM (448 Kbytes) for Cortex®-M4. | ||
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| - ST PMIC STPMIC1A | ||
| - 4-Gbit DDR3L, 16 bits, 533 MHz | ||
| - 1-Gbps Ethernet (RGMII) compliant with IEEE-802.3ab | ||
| - USB OTG HS | ||
| - Audio CODEC, with a stereo headset jack, including analog microphone input | ||
| - 4 user LEDs | ||
| - 2 user and reset push-buttons, 1 wake-up button | ||
| - 5 V / 3 A USB Type-CTM power supply input (not provided) | ||
| - Board connectors: | ||
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| - Ethernet RJ45 | ||
| - 4 USB Host Type-A | ||
| - USB Type-C | ||
| - DRP MIPI DSI HDMI | ||
| - Stereo headset jack including analog microphone input | ||
| - microSD card | ||
| - GPIO expansion connector (Raspberry Pi® shields capability) | ||
| - ArduinoTM Uno V3 expansion connectors | ||
| - On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration | ||
| capability: Virtual COM port and debug port | ||
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| - Board-specific features: | ||
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| - 4" TFT 480×800 pixels with LED backlight, MIPI DSI interface, and capacitive | ||
| touch panel | ||
| - Wi-Fi® 802.11b/g/n | ||
| - Bluetooth® Low Energy 4.1 | ||
|
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| .. image:: img/en.stm32mp157c-dk2.jpg | ||
| :width: 600px | ||
| :align: center | ||
| :height: 526px | ||
| :alt: STM32MP157C-DK2 Discovery | ||
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| More information about the board can be found at the | ||
| `STM32P157C Discovery website`_. | ||
|
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| Hardware | ||
| ******** | ||
|
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| The STM32MP157 SoC provides the following hardware capabilities: | ||
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| - Core: | ||
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| - 32-bit dual-core Arm® Cortex®-A7 | ||
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| - L1 32-Kbyte I / 32-Kbyte D for each core | ||
| - 256-Kbyte unified level 2 cache | ||
| - Arm® NEON™ and Arm® TrustZone® | ||
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| - 32-bit Arm® Cortex®-M4 with FPU/MPU | ||
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| - Up to 209 MHz (Up to 703 CoreMark®) | ||
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| - Memories: | ||
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| - External DDR memory up to 1 Gbyte. | ||
| - 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM + | ||
| 64 KB of AHB SRAM in backup domain. | ||
| - Dual mode Quad-SPI memory interface | ||
| - Flexible external memory controller with up to 16-bit data bus | ||
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| - Security/safety: | ||
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| - Secure boot, TrustZone® peripherals with Cortex®-M4 resources isolation | ||
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| - Clock management: | ||
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| - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz | ||
| LSI oscillator | ||
| - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator | ||
| - 6 × PLLs with fractional mode | ||
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| - General-purpose input/outputs: | ||
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| - Up to 176 I/O ports with interrupt capability | ||
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| - Interconnect matrix | ||
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| - 3 DMA controllers | ||
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| - Communication peripherals: | ||
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| - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus) | ||
| - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) | ||
| - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy) | ||
| - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx) | ||
| - SPDIF Rx with 4 inputs | ||
| - HDMI-CEC interface | ||
| - MDIO Slave interface | ||
| - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO) | ||
| - 2 × CAN controllers supporting CAN FD protocol, TTCAN capiblity | ||
| - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously | ||
| - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI) | ||
| - 8- to 14-bit camera interface up to 140 Mbyte/s | ||
| - 6 analog peripherals | ||
| - 2 × ADCs with 16-bit max. resolution. | ||
| - 1 × temperature sensor | ||
| - 2 × 12-bit D/A converters (1 MHz) | ||
| - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6 | ||
| filters | ||
| - Internal or external ADC/DAC reference VREF+ | ||
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| - Graphics: | ||
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| - 3D GPU: Vivante® - OpenGL® ES 2.0 | ||
| - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps | ||
| - MIPI® DSI 2 data lanes up to 1 GHz each | ||
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| - Timers: | ||
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| - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature | ||
| (incremental) encoder input | ||
| - 2 × 16-bit advanced motor control timers | ||
| - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM) | ||
| - 5 × 16-bit low-power timers | ||
| - RTC with sub-second accuracy and hardware calendar | ||
| - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor) | ||
| - 1 × SysTick Cortex®-M4 timer | ||
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| - Hardware acceleration: | ||
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| - AES 128, 192, 256, TDES | ||
| - HASH (MD5, SHA-1, SHA224, SHA256), HMAC | ||
| - 2 × true random number generator (3 oscillators each) | ||
| - 2 × CRC calculation unit | ||
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| - Debug mode: | ||
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| - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces | ||
| - 8-Kbyte embedded trace buffer | ||
| - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user | ||
|
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| More information about STM32P157C can be found here: | ||
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| - `STM32MP157C on www.st.com`_ | ||
| - `STM32MP157C reference manual`_ | ||
|
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| Supported Features | ||
| ================== | ||
|
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| The Zephyr stm32mp157c_dk2 board configuration supports the following hardware | ||
| features: | ||
|
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| +-----------+------------+-------------------------------------+ | ||
| | Interface | Controller | Driver/Component | | ||
| +===========+============+=====================================+ | ||
| | NVIC | on-chip | nested vector interrupt controller | | ||
| +-----------+------------+-------------------------------------+ | ||
|
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| The default configuration can be found in the defconfig file: | ||
| ``boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig`` | ||
|
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| Connections and IOs | ||
| =================== | ||
|
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| STM32MP157C-DK2 Discovery Board schematic is available here: | ||
| `STM32MP157C Discovery board schematics`_. | ||
|
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|
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| System Clock | ||
| ------------ | ||
|
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| The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. | ||
|
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| Serial Port | ||
| ----------- | ||
|
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| The STM32MP157C-DK2 Discovery board has 8 U(S)ARTs. | ||
| The Zephyr console output is assigned by default to the ram console to be dumped | ||
| by the Linux Remoteproc Framework on Cortex®-A7 core. The UART 4 can enabled as | ||
| Cortex®-M4 console. | ||
|
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| Programming and Debugging | ||
| ************************* | ||
| The STM32MP157C doesn't have QSPI flash for the Cortex®-M4 and it needs to be | ||
| started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the | ||
| Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset. | ||
| The Cortex®-A7 can perform these steps at bootloader level or after the Linux | ||
| system has booted. | ||
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| The Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at | ||
| address 0x00000000 (RETRAM), the vector table should be loaded at this address | ||
| These are the memory mappings for Cortex®-A7 and Cortex®-M4: | ||
|
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| +------------+-----------------------+------------------------+----------------+ | ||
| | Region | Cortex®-A7 | Cortex®-M4 | Size | | ||
| +============+=======================+========================+================+ | ||
| | RETRAM | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF | 64KB | | ||
| +------------+-----------------------+------------------------+----------------+ | ||
| | MCUSRAM | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF | 384KB | | ||
| +------------+-----------------------+------------------------+----------------+ | ||
| | DDR | 0xC0000000-0xFFFFFFFF | | up to 1 GB | | ||
| +------------+-----------------------+------------------------+----------------+ | ||
|
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| Refer to `stm32mp157c boot Cortex-M4 firmware`_ wiki page for instruction | ||
| to load and start the Cortex-M4 firmware. | ||
|
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| Debugging | ||
| ========= | ||
|
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| You can debug an application using OpenOCD and GDB. The Solution proposed below | ||
| is based on the Linux STM32MP1 SDK OpenOCD and is available only for a Linux | ||
| environment. The firmware must first be loaded by the Cortex®-A7. Developer | ||
| then attachs the debugger to the running Zephyr using OpenOCD. | ||
|
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| Prerequisite | ||
| ------------ | ||
| install `stm32mp1 developer package`_. | ||
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| 1) start OpenOCD in a dedicated terminal | ||
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| - Start up the sdk environment:: | ||
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| source <SDK installation directory>/environment-setup-cortexa7hf-neon-vfpv4-openstlinux_weston-linux-gnueabi | ||
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| - Start OpenOCD:: | ||
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| ${OECORE_NATIVE_SYSROOT}/usr/bin/openocd -s ${OECORE_NATIVE_SYSROOT}/usr/share/openocd/scripts -f board/stm32mp15x_dk2.cfg | ||
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| 2) run gdb in Zephyr environment | ||
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| .. code-block:: console | ||
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| # On Linux | ||
| cd $ZEPHYR_BASE/samples/hello_world | ||
| mkdir -p build && cd build | ||
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| # Use cmake to configure a Ninja-based build system: | ||
| cmake -GNinja -DBOARD=stm32mp157_dk2 .. | ||
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| # Now run ninja on the generated build system: | ||
| ninja debug | ||
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| .. _STM32P157C Discovery website: | ||
| https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-discovery-kits/stm32mp157c-dk2.html | ||
|
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| .. _STM32MP157C Discovery board User Manual: | ||
| https://www.st.com/resource/en/user_manual/dm00591354.pdf | ||
|
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| .. _STM32MP157C Discovery board schematics: | ||
| https://www.st.com/resource/en/schematic_pack/mb1272-dk2-c01_schematic.pdf | ||
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| .. _STM32MP157C on www.st.com: | ||
| https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp157/stm32mp157c.html | ||
|
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| .. _STM32MP157C reference manual: | ||
| https://www.st.com/resource/en/reference_manual/DM00327659.pdf | ||
|
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| .. _stm32mp1 developer package: | ||
| https://wiki.st.com/stm32mpu/index.php/STM32MP1_Developer_Package#Installing_the_SDK | ||
|
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| .. _stm32mp157c boot Cortex-M4 firmware: | ||
| https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework |
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| Original file line number | Diff line number | Diff line change |
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| /* | ||
| * Copyright (c) 2019 STMicroelectronics | ||
| * | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| */ | ||
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| /dts-v1/; | ||
| #include <st/mp1/stm32mp157.dtsi> | ||
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| / { | ||
| model = "STMicroelectronics STM32MP157-DK2 board"; | ||
| compatible = "st,stm32mp157c-dk2", "st,stm32mp15"; | ||
| chosen { | ||
| zephyr,flash = &retram; | ||
| zephyr,sram = &mcusram; | ||
| }; | ||
| }; |
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| identifier: stm32mp157c_dk2 | ||
| name: STM32MP157C_DK2 | ||
| type: mcu | ||
| arch: arm | ||
| toolchain: | ||
| - zephyr | ||
| - gccarmemb | ||
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|
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| - xtools | ||
| testing: | ||
| ignore_tags: | ||
| - net | ||
| - mpu | ||
| - tinycrypt | ||
| - crypto | ||
| - aes | ||
| - cmm | ||
| - shell | ||
| - LED | ||
| - gpio | ||
| - nfc | ||
| ram: 256 | ||
| flash: 64 | ||
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,15 @@ | ||
| CONFIG_ARM=y | ||
| CONFIG_BOARD_STM32MP157C_DK2=y | ||
| CONFIG_SOC_SERIES_STM32MP1X=y | ||
| CONFIG_SOC_STM32MP15_M4=y | ||
| CONFIG_CORTEX_M_SYSTICK=y | ||
| # 209 MHz system clock | ||
| CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=209000000 | ||
|
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| # clock configuration | ||
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|
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| CONFIG_CLOCK_CONTROL=n | ||
|
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| #remote proc console | ||
| CONFIG_CONSOLE=y | ||
| CONFIG_RAM_CONSOLE=y | ||
| CONFIG_RAM_CONSOLE_BUFFER_SIZE=1024 | ||
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