zephyrproject-rtos · galak · May 7, 2021 · Mar 31, 2021 · Mar 30, 2021 · Mar 31, 2021
diff --git a/arch/arc/CMakeLists.txt b/arch/arc/CMakeLists.txt
@@ -12,8 +12,11 @@ zephyr_cc_option(-fno-delete-null-pointer-checks)
 
 zephyr_cc_option_ifdef(CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS -munaligned-access)
 
-# Instruct compiler to use register R26 as thread pointer
-# for thread local storage.
-zephyr_cc_option_ifdef(CONFIG_THREAD_LOCAL_STORAGE -mtp-regno=26)
+if(CONFIG_ISA_ARCV2)
+  # Instruct compiler to use register R26 as thread pointer
+  # for thread local storage.
+  # For ARCv3 the register is fixed to r30, so we don't need to specify it
+  zephyr_cc_option_ifdef(CONFIG_THREAD_LOCAL_STORAGE -mtp-regno=26)
+endif()
 
 add_subdirectory(core)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
@@ -39,6 +39,11 @@ config ISA_ARCV2
 	help
 	  v2 ISA for the ARC-HS & ARC-EM cores
 
+config ISA_ARCV3
+	bool "ARC ISA v3"
+	select USE_SWITCH
+	select USE_SWITCH_SUPPORTED
+
 endchoice
 
 if ISA_ARCV2
@@ -83,11 +88,34 @@ config CPU_HS3X
 
 endif #ISA_ARCV2
 
+if ISA_ARCV3
+
+config CPU_HS6X
+	bool
+	select CPU_ARCHS
+	select 64BIT
+	help
+	  If y, the SoC uses an ARC HS6x CPU
+
+endif #ISA_ARCV3
+
 config FP_FPU_DA
 	bool
 
 menu "ARC CPU Options"
 
+config ARC_HAS_ZOL
+	bool
+	depends on ISA_ARCV2
+	default y
+	help
+	  ARCv2 CPUs have ZOL hardware loop mechanism which the ARCv3 ISA drops.
+	  Architecturally ZOL provides
+	  - LPcc instruction
+	  - LP_COUNT core reg
+	  - LP_START, LP_END aux regs
+	  Disabling this option removes usage of ZOL regs from code
+
 config NUM_IRQ_PRIO_LEVELS
 	int "Number of supported interrupt priority levels"
 	range 1 16
@@ -123,6 +151,7 @@ config RGF_NUM_BANKS
 
 config ARC_FIRQ
 	bool "FIRQ enable"
+	depends on ISA_ARCV2
 	default y
 	help
 	  Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts
@@ -147,6 +176,7 @@ config ARC_FIRQ_STACK_SIZE
 
 config ARC_HAS_STACK_CHECKING
 	bool "ARC has STACK_CHECKING"
+	depends on ISA_ARCV2
 	default y
 	help
 	  ARC is configured with STACK_CHECKING which is a mechanism for
@@ -233,6 +263,7 @@ config ARC_HAS_ACCL_REGS
 
 config ARC_HAS_SECURE
 	bool "ARC has SecureShield"
+	depends on ISA_ARCV2
 	select CPU_HAS_TEE
 	select ARCH_HAS_TRUSTED_EXECUTION
 	help
@@ -320,3 +351,15 @@ config ARC_EXCEPTION_DEBUG
 	  strings.
 
 endmenu
+
+config MAIN_STACK_SIZE
+	default 4096 if 64BIT
+
+config TEST_EXTRA_STACKSIZE
+	default 1024 if 64BIT
+
+config CMSIS_THREAD_MAX_STACK_SIZE
+	default 1024 if 64BIT
+
+config CMSIS_V2_THREAD_MAX_STACK_SIZE
+	default 1024 if 64BIT
diff --git a/arch/arc/core/cpu_idle.S b/arch/arc/core/cpu_idle.S
@@ -16,6 +16,7 @@
 #include <toolchain.h>
 #include <linker/sections.h>
 #include <arch/cpu.h>
+#include <arch/arc/asm-compat/assembler.h>
 
 GTEXT(arch_cpu_idle)
 GTEXT(arch_cpu_atomic_idle)
@@ -36,11 +37,12 @@ SECTION_VAR(BSS, z_arc_cpu_sleep_mode)
 SECTION_FUNC(TEXT, arch_cpu_idle)
 
 #ifdef CONFIG_TRACING
-	push_s blink
+	PUSHR blink
 	jl    sys_trace_idle
-	pop_s blink
+	POPR blink
 #endif
 
+	/* z_arc_cpu_sleep_mode is 32 bit despite of platform bittnes */
 	ld r1, [z_arc_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1
@@ -57,11 +59,12 @@ SECTION_FUNC(TEXT, arch_cpu_idle)
 SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
 
 #ifdef CONFIG_TRACING
-	push_s blink
+	PUSHR blink
 	jl    sys_trace_idle
-	pop_s blink
+	POPR blink
 #endif
 
+	/* z_arc_cpu_sleep_mode is 32 bit despite of platform bittnes */
 	ld r1, [z_arc_cpu_sleep_mode]
 	or r1, r1, (1 << 4) /* set IRQ-enabled bit */
 	sleep r1

diff --git a/arch/arc/core/fatal.c b/arch/arc/core/fatal.c
@@ -24,17 +24,19 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 #ifdef CONFIG_ARC_EXCEPTION_DEBUG
 static void dump_arc_esf(const z_arch_esf_t *esf)
 {
-	LOG_ERR(" r0: 0x%08x  r1: 0x%08x  r2: 0x%08x  r3: 0x%08x",
+	LOG_ERR(" r0: 0x%" PRIxPTR "  r1: 0x%" PRIxPTR "  r2: 0x%" PRIxPTR "  r3: 0x%" PRIxPTR "",
 		esf->r0, esf->r1, esf->r2, esf->r3);
-	LOG_ERR(" r4: 0x%08x  r5: 0x%08x  r6: 0x%08x  r7: 0x%08x",
+	LOG_ERR(" r4: 0x%" PRIxPTR "  r5: 0x%" PRIxPTR "  r6: 0x%" PRIxPTR "  r7: 0x%" PRIxPTR "",
 		esf->r4, esf->r5, esf->r6, esf->r7);
-	LOG_ERR(" r8: 0x%08x  r9: 0x%08x r10: 0x%08x r11: 0x%08x",
+	LOG_ERR(" r8: 0x%" PRIxPTR "  r9: 0x%" PRIxPTR " r10: 0x%" PRIxPTR " r11: 0x%" PRIxPTR "",
 		esf->r8, esf->r9, esf->r10, esf->r11);
-	LOG_ERR("r12: 0x%08x r13: 0x%08x  pc: 0x%08x",
+	LOG_ERR("r12: 0x%" PRIxPTR " r13: 0x%" PRIxPTR "  pc: 0x%" PRIxPTR "",
 		esf->r12, esf->r13, esf->pc);
-	LOG_ERR(" blink: 0x%08x status32: 0x%08x", esf->blink, esf->status32);
-	LOG_ERR("lp_end: 0x%08x lp_start: 0x%08x lp_count: 0x%08x",
+	LOG_ERR(" blink: 0x%" PRIxPTR " status32: 0x%" PRIxPTR "", esf->blink, esf->status32);
+#ifdef CONFIG_ARC_HAS_ZOL
+	LOG_ERR("lp_end: 0x%" PRIxPTR " lp_start: 0x%" PRIxPTR " lp_count: 0x%" PRIxPTR "",
 		esf->lp_end, esf->lp_start, esf->lp_count);
+#endif /* CONFIG_ARC_HAS_ZOL */
 }
 #endif
 

diff --git a/arch/arc/core/fault_s.S b/arch/arc/core/fault_s.S
@@ -17,6 +17,7 @@
 #include <arch/cpu.h>
 #include <swap_macros.h>
 #include <syscall.h>
+#include <arch/arc/asm-compat/assembler.h>
 
 GTEXT(_Fault)
 GTEXT(__reset)
@@ -43,10 +44,10 @@ GTEXT(z_irq_do_offload);
 	lr r0,[_ARC_V2_ERSEC_STAT]
 	st_s r0, [sp, ___isf_t_sec_stat_OFFSET]
 #endif
-	lr r0,[_ARC_V2_ERET]
-	st_s r0, [sp, ___isf_t_pc_OFFSET]
-	lr r0,[_ARC_V2_ERSTATUS]
-	st_s r0, [sp, ___isf_t_status32_OFFSET]
+	LRR r0, [_ARC_V2_ERET]
+	STR r0, sp, ___isf_t_pc_OFFSET
+	LRR r0, [_ARC_V2_ERSTATUS]
+	STR r0, sp, ___isf_t_status32_OFFSET
 .endm
 
 /*
@@ -84,9 +85,9 @@ _exc_entry:
 	 * and exception is raised, then here it's guaranteed that
 	 * exception handling has necessary stack to use
 	 */
-	mov ilink, sp
+	MOVR ilink, sp
 	_get_curr_cpu_irq_stack sp
-	sub sp, sp, (CONFIG_ISR_STACK_SIZE - CONFIG_ARC_EXCEPTION_STACK_SIZE)
+	SUBR sp, sp, (CONFIG_ISR_STACK_SIZE - CONFIG_ARC_EXCEPTION_STACK_SIZE)
 
 	/*
 	 * save caller saved registers
@@ -102,9 +103,9 @@ _exc_entry:
 	_save_exc_regs_into_stack
 
 	/* sp is parameter of _Fault */
-	mov_s r0, sp
+	MOVR r0, sp
 	/* ilink is the thread's original sp */
-	mov r1, ilink
+	MOVR r1, ilink
 	jl _Fault
 
 _exc_return:
@@ -118,9 +119,9 @@ _exc_return:
 
 	_get_next_switch_handle
 
-	breq r0, r2, _exc_return_from_exc
+	BREQR r0, r2, _exc_return_from_exc
 
-	mov_s r2, r0
+	MOVR r2, r0
 
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	/*
@@ -145,8 +146,8 @@ _exc_return:
 	 */
 	mov ilink, r2
 #endif
-	lr r3, [_ARC_V2_STATUS32]
-	and r3,r3,(~(_ARC_V2_STATUS32_AE | _ARC_V2_STATUS32_RB(7)))
+	LRR r3, [_ARC_V2_STATUS32]
+	ANDR r3, r3, (~(_ARC_V2_STATUS32_AE | _ARC_V2_STATUS32_RB(7)))
 	kflag r3
 	/* pretend lowest priority interrupt happened to use common handler
 	 * if exception is raised in irq, i.e., _ARC_V2_AUX_IRQ_ACT !=0,
@@ -158,7 +159,7 @@ _exc_return:
 #ifdef CONFIG_ARC_SECURE_FIRMWARE
 	mov_s r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
 #else
-	mov_s r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
+	MOVR r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
 #endif
 
 #ifdef CONFIG_ARC_NORMAL_FIRMWARE
@@ -169,7 +170,7 @@ _exc_return:
 	sjli SJLI_CALL_ARC_SECURE
 	pop_s r2
 #else
-	sr r3, [_ARC_V2_AUX_IRQ_ACT]
+	SRR r3, [_ARC_V2_AUX_IRQ_ACT]
 #endif
 
 #if defined(CONFIG_ARC_FIRQ) && CONFIG_RGF_NUM_BANKS != 1
@@ -183,18 +184,18 @@ _exc_return_from_exc:
 	/* exception handler may change return address.
 	 * reload it
 	 */
-	ld_s r0, [sp, ___isf_t_pc_OFFSET]
-	sr r0, [_ARC_V2_ERET]
+	LDR r0, sp, ___isf_t_pc_OFFSET
+	SRR r0, [_ARC_V2_ERET]
 
 	_pop_irq_stack_frame
-	mov sp, ilink
+	MOVR sp, ilink
 	rtie
 
 /* separated entry for trap which may be used by irq_offload, USERPSACE */
 SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
 	/* get the id of trap_s */
-	lr ilink, [_ARC_V2_ECR]
-	and ilink, ilink, 0x3f
+	LRR ilink, [_ARC_V2_ECR]
+	ANDR ilink, ilink, 0x3f
 #ifdef CONFIG_USERSPACE
 	cmp ilink, _TRAP_S_CALL_SYSTEM_CALL
 	bne _do_non_syscall_trap
@@ -236,7 +237,7 @@ _do_non_syscall_trap:
 	 * so its entry is different with normal exception handling, it is
 	 * handled in isr stack
 	 */
-	cmp ilink, _TRAP_S_SCALL_IRQ_OFFLOAD
+	CMPR ilink, _TRAP_S_SCALL_IRQ_OFFLOAD
 	bne _exc_entry
 	/* save caller saved registers */
 	_create_irq_stack_frame
@@ -247,15 +248,15 @@ _do_non_syscall_trap:
 	_check_and_inc_int_nest_counter r0, r1
 
 	bne.d exc_nest_handle
-	mov_s r0, sp
+	MOVR r0, sp
 
 	_get_curr_cpu_irq_stack sp
 exc_nest_handle:
-	push_s r0
+	PUSHR r0
 
 	jl z_irq_do_offload
 
-	pop sp
+	POPR sp
 
 	_dec_int_nest_counter r0, r1