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Add nxp edac driver #94111
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Add nxp edac driver #94111
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Hello @yvesll, and thank you very much for your first pull request to the Zephyr project! |
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Looks like a very good first PR. But can you explain why this Devicetree structure with 4(+?) nodes was chosen?
You are correct, the virtual edac node and independent eim channel binding are redundant here. |
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Please fix the issue in "Quality Gate passed". |
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@yvesll you might need to rebase to get past some twister bug |
Sure, I will do this together with the support for MCXE31 |
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| /* Callback data provided to function passed to notify_cb_set */ | ||
| struct edac_nxp_callback_data { | ||
| /* Number of corrected errors */ | ||
| uint8_t corr_err_count; |
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If the corr_err_count could exceed 255, then should use uint32_t.
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It will not, ERM only use 8 bit for error counter.
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| static void edac_nxp_irq_0(const struct device *dev) | ||
| { | ||
| IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 0, irq), DT_INST_IRQ_BY_IDX(0, 0, priority), edac_nxp_isr, |
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Hardcode the irq to 2. Considering the update for all IRQ numbers
| IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 0, irq), DT_INST_IRQ_BY_IDX(0, 0, priority), edac_nxp_isr, | |
| #include <zephyr/sys/util.h> | |
| static void edac_nxp_irq_0(const struct device *dev) | |
| { | |
| IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 0, irq), DT_INST_IRQ_BY_IDX(0, 0, priority), edac_nxp_isr, | |
| DEVICE_DT_INST_GET(0), 0); | |
| irq_enable(DT_INST_IRQ_BY_IDX(0, 0, irq)); | |
| IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 1, irq), DT_INST_IRQ_BY_IDX(0, 1, priority), edac_nxp_isr, | |
| DEVICE_DT_INST_GET(0), 0); | |
| irq_enable(DT_INST_IRQ_BY_IDX(0, 1, irq)); | |
| } | |
| #define ERM_IRQ_CONNECT_IDX(idx, n) \ | |
| do { \ | |
| IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, idx, irq), \ | |
| DT_INST_IRQ_BY_IDX(n, idx, priority), \ | |
| edac_nxp_isr, DEVICE_DT_INST_GET(n), 0); \ | |
| irq_enable(DT_INST_IRQ_BY_IDX(n, idx, irq)); \ | |
| } while (0) | |
| static void edac_nxp_irq_0(const struct device *dev) | |
| { | |
| ARG_UNUSED(dev); | |
| UTIL_LISTIFY(DT_INST_NUM_IRQS(0), ERM_IRQ_CONNECT_IDX, 0); | |
| } | |
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No platform has more than one erm/eim instance now. It only requires one instance as 31 channels is really enough for MCU.
Add edac driver for NXP's ERM and EIM peripherals. It can inject ECC error to specific channel within EIM and then report the error address, syndrome and count within ERM. Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Add eim, erm and edac instance for frdm_mcxa153, frdm_mcxn236, frdm_mcxn947, frdm_mcxe247 and frdm_mcxe31b. Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Decouple the edac sample with IBECC. Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
Update the console log in readme to make it aligned with the actual output Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
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Added NXP's EDAC implementation based on EIM and ERM