enable ethernet support on the stm32mp135f-dk

arch/arm/core/mmu/arm_mmu.c

@@ -891,6 +891,17 @@ static int __arch_mem_map(void *virt, uintptr_t phys, size_t size, uint32_t flag
 	switch (flags & K_MEM_CACHE_MASK) {
 
 	case K_MEM_CACHE_NONE:
+		switch (flags & K_MEM_ARM_NC_TYPE_MASK) {
+		case K_MEM_ARM_STRONGLY_ORDERED_NC:
+			conv_flags |= MT_STRONGLY_ORDERED;
+			break;
+		case K_MEM_ARM_NORMAL_NC:
+			conv_flags |= MT_NORMAL;
+			break;
+		default:
+			conv_flags |= MT_DEVICE;
+		}
+		break;
 	default:
 		conv_flags |= MT_DEVICE;
 		break;

boards/st/stm32mp135f_dk/Kconfig.defconfig

@@ -12,4 +12,7 @@ config GPIO_MCP230XX_INIT_PRIORITY
 
 endif # GPIO_MCP230XX
 
+config NET_L2_ETHERNET
+	default y if NETWORKING
+
 endif # BOARD_STM32MP135F_DK

boards/st/stm32mp135f_dk/stm32mp135f_dk.dts

@@ -73,6 +73,13 @@
 		gpio-map = <CSI_IO0 0 &mcp23017 4 0>,
 			   <CSI_IO1 0 &mcp23017 3 0>;
 	};
+
+	eth_ram: sram@30000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x2FFE0000 DT_SIZE_K(16)>;
+		#memory-region-cells = <0>;
+		zephyr,memory-region = "ETH_SRAM";
+	};
 };
 
 &clk_hsi {
@@ -111,6 +118,17 @@
 	status = "okay";
 };
 
+&pll4 {
+	clocks = <&clk_hsi>;
+	div-m = <2>;
+	mul-n = <50>;
+	div-p = <12>;
+	div-q = <60>;
+	div-r = <6>;
+	fracn = <0>;
+	status = "okay";
+};
+
 &rcc {
 	clock-frequency = <DT_FREQ_M(1000)>;
 	clocks = <&pll>;
@@ -250,3 +268,30 @@ csi_interface: &dcmipp {
 
 	status = "disabled";
 };
+
+&mac {
+	status = "okay";
+	pinctrl-0 = <&eth1_txd0_pg13
+		     &eth1_txd1_pg14
+		     &eth1_tx_ctl_pb11
+		     &eth1_ref_clk_pa1
+		     &eth1_rxd0_pc4
+		     &eth1_rxd1_pc5
+		     &eth1_crs_dv_pc1>;
+	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+	memory-regions = <&eth_ram>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth1_mdio_pa2 &eth1_mdc_pg2>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "microchip,lan8742";
+		reg = <0>;
+		reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>;
+	};
+};

drivers/ethernet/Kconfig.stm32_hal

@@ -26,8 +26,8 @@ choice ETH_STM32_HAL_API_VERSION
 
 config ETH_STM32_HAL_API_V2
 	bool "Use official STM32Cube HAL driver"
-	depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32N6X
-	select USE_STM32_HAL_ETH_EX if SOC_SERIES_STM32N6X
+	depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32N6X || SOC_SERIES_STM32MP13X
+	select USE_STM32_HAL_ETH_EX if SOC_SERIES_STM32N6X || SOC_SERIES_STM32MP13X
 	help
 	  Use the official STM32Cube HAL driver instead of the legacy one.
 

drivers/ethernet/eth_stm32_hal_common.c

@@ -431,6 +431,18 @@ static const struct eth_stm32_hal_dev_cfg eth0_config = {
 #if DT_INST_CLOCKS_HAS_NAME(0, mac_clk_ptp)
 	.pclken_ptp = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_ptp, bus),
 		       .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_ptp, bits)},
+#endif
+#if DT_INST_CLOCKS_HAS_NAME(0, mac_clk)
+	.pclken_mac = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk, bus),
+		       .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk, bits)},
+#endif
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32mp13_ethernet)
+	.clockselection = DT_NODE_HAS_PROP(0, st_ext_phyclk) ? HAL_ETH1_REF_CLK_RCC
+							     : HAL_ETH1_REF_CLK_RX_CLK_PIN,
+#endif
+#if DT_INST_CLOCKS_HAS_NAME(0, eth_ker)
+	.pclken_ker = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, eth_ker, bus),
+		       .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, eth_ker, bits)},
 #endif
 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
 };

drivers/ethernet/eth_stm32_hal_priv.h

@@ -9,6 +9,7 @@
 
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <zephyr/linker/devicetree_regions.h>
 #include <zephyr/kernel.h>
 #include <zephyr/net/ethernet.h>
 #include <zephyr/net/phy.h>
@@ -36,6 +37,11 @@ extern const struct device *eth_stm32_phy_dev;
 #elif defined(CONFIG_SOC_SERIES_STM32H7X)
 #define __eth_stm32_desc __attribute__((section(".eth_stm32_desc")))
 #define __eth_stm32_buf  __attribute__((section(".eth_stm32_buf")))
+#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
+#define ETH_DMA_REGION  DT_PHANDLE(DT_NODELABEL(mac), memory_regions)
+#define ETH_DMA_LINKER_REGION_NAME LINKER_DT_NODE_REGION_NAME(ETH_DMA_REGION)
+#define __eth_stm32_desc ALIGN_32BYTES(__attribute__((__section__(ETH_DMA_LINKER_REGION_NAME))))
+#define __eth_stm32_buf  ALIGN_32BYTES(__attribute__((__section__(ETH_DMA_LINKER_REGION_NAME))))
 #elif defined(CONFIG_NOCACHE_MEMORY)
 #define __eth_stm32_desc __nocache __aligned(4)
 #define __eth_stm32_buf  __nocache __aligned(4)
@@ -102,6 +108,15 @@ extern ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB];
 struct eth_stm32_hal_dev_cfg {
 	void (*config_func)(void);
 	struct stm32_pclken pclken;
+#if DT_INST_CLOCKS_HAS_NAME(0, mac_clk)
+	struct stm32_pclken pclken_mac;
+#endif
+#if DT_INST_CLOCKS_HAS_NAME(0, eth_ker)
+	struct stm32_pclken pclken_ker;
+#endif
+#if defined(CONFIG_SOC_SERIES_STM32MP13X)
+	ETH_ClkSrcTypeDef clockselection;
+#endif /* CONFIG_SOC_SERIES_STM32MP13X */
 	struct stm32_pclken pclken_rx;
 	struct stm32_pclken pclken_tx;
 #if DT_INST_CLOCKS_HAS_NAME(0, mac_clk_ptp)

drivers/ethernet/eth_stm32_hal_v2.c

@@ -10,6 +10,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/__assert.h>
 #include <ethernet/eth_stats.h>
+#include <zephyr/linker/devicetree_regions.h>
 
 #include <errno.h>
 #include <stdbool.h>
@@ -32,7 +33,7 @@ struct eth_stm32_tx_buffer_header {
 	bool used;
 };
 
-static ETH_TxPacketConfig tx_config;
+static ETH_TxPacketConfigTypeDef tx_config;
 
 static struct eth_stm32_rx_buffer_header dma_rx_buffer_header[ETH_RXBUFNB];
 static struct eth_stm32_tx_buffer_header dma_tx_buffer_header[ETH_TXBUFNB];
@@ -41,7 +42,11 @@ static struct eth_stm32_tx_context dma_tx_context[ETH_TX_DESC_CNT];
 /* Pointer to an array of ETH_STM32_RX_BUF_SIZE uint8_t's */
 typedef uint8_t (*RxBufferPtr)[ETH_STM32_RX_BUF_SIZE];
 
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32mp13_ethernet)
+void HAL_ETH_RxAllocateCallback(ETH_HandleTypeDef *heth, uint8_t **buf)
+#else
 void HAL_ETH_RxAllocateCallback(uint8_t **buf)
+#endif
 {
 	for (size_t i = 0; i < ETH_RXBUFNB; ++i) {
 		if (!dma_rx_buffer_header[i].used) {
@@ -56,7 +61,12 @@ void HAL_ETH_RxAllocateCallback(uint8_t **buf)
 }
 
 /* called by HAL_ETH_ReadData() */
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32mp13_ethernet)
+void HAL_ETH_RxLinkCallback(ETH_HandleTypeDef *heth, void **pStart, void **pEnd,
+			    uint8_t *buff, uint16_t Length)
+#else
 void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
+#endif
 {
 	/* buff points to the begin on one of the rx buffers,
 	 * so we can compute the index of the given buffer
@@ -81,7 +91,11 @@ void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t
 }
 
 /* Called by HAL_ETH_ReleaseTxPacket */
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32mp13_ethernet)
+void HAL_ETH_TxFreeCallback(ETH_HandleTypeDef *heth, uint32_t *buff)
+#else
 void HAL_ETH_TxFreeCallback(uint32_t *buff)
+#endif
 {
 	__ASSERT_NO_MSG(buff != NULL);
 
@@ -279,7 +293,11 @@ int eth_stm32_tx(const struct device *dev, struct net_pkt *pkt)
 		HAL_ETH_ReleaseTxPacket(heth);
 	} else {
 		/* We need to release the tx context and its buffers */
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32mp13_ethernet)
+		HAL_ETH_TxFreeCallback(heth, (uint32_t *)ctx);
+#else
 		HAL_ETH_TxFreeCallback((uint32_t *)ctx);
+#endif
 	}
 
 	k_mutex_unlock(&dev_data->tx_mutex);
@@ -454,6 +472,9 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
 	dev_data->stats.error_details.rx_crc_errors = heth->Instance->MMCRCRCEPR;
 	dev_data->stats.error_details.rx_align_errors = heth->Instance->MMCRAEPR;
+#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32mp13_ethernet)
+	dev_data->stats.error_details.rx_crc_errors = heth->Instance->MMCRXCRCEPR;
+	dev_data->stats.error_details.rx_align_errors = heth->Instance->MMCRXAEPR;
 #else
 	dev_data->stats.error_details.rx_crc_errors = heth->Instance->MMCRFCECR;
 	dev_data->stats.error_details.rx_align_errors = heth->Instance->MMCRFAECR;
@@ -467,6 +488,9 @@ int eth_stm32_hal_init(const struct device *dev)
 	struct eth_stm32_hal_dev_data *dev_data = dev->data;
 	ETH_HandleTypeDef *heth = &dev_data->heth;
 	HAL_StatusTypeDef hal_ret = HAL_OK;
+	__maybe_unused const struct eth_stm32_hal_dev_cfg *cfg = dev->config;
+	__maybe_unused uint8_t *desc_uncached_addr;
+	__maybe_unused int ret;
 
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
 	for (int ch = 0; ch < ETH_DMA_CH_CNT; ch++) {
@@ -479,6 +503,37 @@ int eth_stm32_hal_init(const struct device *dev)
 #endif
 	heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE;
 
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32mp13_ethernet)
+	/* Map memory region for DMA descriptor and buffer as non cacheable */
+	k_mem_map_phys_bare(&desc_uncached_addr,
+			    DT_REG_ADDR(ETH_DMA_REGION),
+			    DT_REG_SIZE(ETH_DMA_REGION),
+			    K_MEM_PERM_RW | K_MEM_DIRECT_MAP | K_MEM_CACHE_NONE |
+			    K_MEM_ARM_NORMAL_NC);
+
+	heth->Init.ClockSelection = cfg->clockselection;
+#endif
+
+#if DT_INST_CLOCKS_HAS_NAME(0, eth_ker)
+	/* Turn on DCMIPP peripheral clock */
+	ret = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+				      (clock_control_subsys_t)&cfg->pclken_ker,
+				      NULL);
+	if (ret < 0) {
+		LOG_ERR("Failed to configure ETH kernel clock. Error %d", ret);
+		return ret;
+	}
+#endif
+
+#if DT_INST_CLOCKS_HAS_NAME(0, mac_clk)
+	ret = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+			       (clock_control_subsys_t)&cfg->pclken_mac);
+	if (ret < 0) {
+		LOG_ERR("Failed to configure mac clock. Error %d", ret);
+		return ret;
+	}
+#endif
+
 	hal_ret = HAL_ETH_Init(heth);
 	if (hal_ret == HAL_TIMEOUT) {
 		/* HAL Init time out. This could be linked to */
@@ -507,7 +562,7 @@ int eth_stm32_hal_init(const struct device *dev)
 	k_sem_init(&dev_data->tx_int_sem, 0, K_SEM_MAX_LIMIT);
 
 	/* Tx config init: */
-	memset(&tx_config, 0, sizeof(ETH_TxPacketConfig));
+	memset(&tx_config, 0, sizeof(ETH_TxPacketConfigTypeDef));
 	tx_config.Attributes = ETH_TX_PACKETS_FEATURES_CSUM |
 				ETH_TX_PACKETS_FEATURES_CRCPAD;
 	tx_config.ChecksumCtrl = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ?

drivers/ethernet/phy/CMakeLists.txt

@@ -6,6 +6,7 @@ zephyr_library_sources_ifdef(CONFIG_PHY_GENERIC_MII	phy_mii.c)
 zephyr_library_sources_ifdef(CONFIG_PHY_ADIN2111	phy_adin2111.c)
 zephyr_library_sources_ifdef(CONFIG_PHY_DM8806	phy_dm8806.c)
 zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_KSZ8081	phy_microchip_ksz8081.c)
+zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_LAN8742 phy_microchip_lan8742.c)
 zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_T1S phy_microchip_t1s.c)
 zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_VSC8541 phy_microchip_vsc8541.c)
 zephyr_library_sources_ifdef(CONFIG_PHY_OA_TC14_PLCA_LIB phy_oa_tc14_plca.c)

drivers/ethernet/phy/Kconfig

@@ -55,6 +55,15 @@ config PHY_MICROCHIP_KSZ8081
 	help
 	  Enable Microchip KSZ8081 Ethernet PHY Driver
 
+config PHY_MICROCHIP_LAN8742
+	bool "Microchip LAN8742 PHY Driver"
+	default y
+	depends on DT_HAS_MICROCHIP_LAN8742_ENABLED
+	select MDIO
+	select GPIO if ($(dt_compat_any_has_prop,$(DT_COMPAT_MICROCHIP_LAN8742),reset-gpios))
+	help
+	  Enable Microchip LAN8742 Ethernet PHY Driver
+
 config PHY_MICROCHIP_VSC8541
 	bool "Microchip VSC8541 PHY Driver"
 	default y