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Merged
merged 5 commits into from
Oct 17, 2025
+97 −4
Merged

STM32: add ethernet support to stm32h7rs #97364

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fe4540f
dts: arm: st: h7rs: Add ethernet node to dts
TD-JBL Sep 17, 2025
dbf4335
drivers: ethernet: stm32: Add support for SOC H7RS-Family
TD-JBL Sep 8, 2025
2904f6d
soc: st: stm32: h7rs: Add memory region to MPU region list
TD-JBL Sep 8, 2025
1f24245
boards: st: nucleo_h7s3l8: Add ethernet
TD-JBL Sep 5, 2025
ec482c1
boards: st: nucleo_h7s3l8: Fix format in doc/index.rst
TD-JBL Oct 14, 2025
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3 changes: 2 additions & 1 deletion boards/st/nucleo_h7s3l8/doc/index.rst
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Expand Up @@ -162,6 +162,7 @@ and a ST morpho connector. Board is configured as follows:
- I2C : PB8, PB9
- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI)
- FDCAN1 RX/TX : PD0, PD1
- ETH : A2, A7, B6, G4, G5, G6, G11, G12, G13

System Clock
------------
Expand All @@ -183,7 +184,7 @@ In order to test backup SRAM you may want to disconnect VBAT from VDD. You can
do it by removing ``SB13`` jumper on the back side of the board.

FDCAN
=====
-----

The Nucleo H7S3L8 board does not have any onboard CAN transceiver. In order to
use the FDCAN bus on this board, an external CAN bus transceiver must be
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25 changes: 25 additions & 0 deletions boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts
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Expand Up @@ -175,6 +175,31 @@
status = "okay";
};

&mac {
pinctrl-0 = <&eth_rmii_rxd0_pg4
&eth_rmii_rxd1_pg5
&eth_rmii_ref_clk_pb6
&eth_rmii_crs_dv_pa7
&eth_rmii_tx_en_pg11
&eth_rmii_txd0_pg13
&eth_rmii_txd1_pg12>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&eth_phy>;
status = "okay";
};

&mdio {
pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pg6>;
pinctrl-names = "default";
status = "okay";

eth_phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
};
};

&flash0 {
partitions {
compatible = "fixed-partitions";
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1 change: 1 addition & 0 deletions boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml
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Expand Up @@ -15,4 +15,5 @@ supported:
- octospi
- can
- canfd
- netif:eth
vendor: st
12 changes: 10 additions & 2 deletions drivers/ethernet/Kconfig.stm32_hal
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Expand Up @@ -26,7 +26,12 @@ choice ETH_STM32_HAL_API_VERSION

config ETH_STM32_HAL_API_V2
bool "Use official STM32Cube HAL driver"
depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32N6X
depends on SOC_SERIES_STM32F4X \
|| SOC_SERIES_STM32F7X \
|| SOC_SERIES_STM32H5X \
|| SOC_SERIES_STM32H7X \
|| SOC_SERIES_STM32H7RSX \
|| SOC_SERIES_STM32N6X
select USE_STM32_HAL_ETH_EX if SOC_SERIES_STM32N6X
help
Use the official STM32Cube HAL driver instead of the legacy one.
Expand Down Expand Up @@ -86,7 +91,10 @@ menuconfig PTP_CLOCK_STM32_HAL
default y
depends on PTP_CLOCK || NET_L2_PTP
depends on ETH_STM32_HAL_API_V2
depends on SOC_SERIES_STM32F7X || SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X
depends on SOC_SERIES_STM32F7X \
|| SOC_SERIES_STM32H5X \
|| SOC_SERIES_STM32H7X \
|| SOC_SERIES_STM32H7RSX
help
Enable STM32 PTP clock support.

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2 changes: 1 addition & 1 deletion drivers/ethernet/eth_stm32_hal_priv.h
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Expand Up @@ -33,7 +33,7 @@ extern const struct device *eth_stm32_phy_dev;
DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm))
#define __eth_stm32_desc __dtcm_noinit_section
#define __eth_stm32_buf __dtcm_noinit_section
#elif defined(CONFIG_SOC_SERIES_STM32H7X)
#elif defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H7RSX)
#define __eth_stm32_desc __attribute__((section(".eth_stm32_desc")))
#define __eth_stm32_buf __attribute__((section(".eth_stm32_buf")))
#elif defined(CONFIG_NOCACHE_MEMORY)
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23 changes: 23 additions & 0 deletions dts/arm/st/h7rs/stm32h7rs.dtsi
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Expand Up @@ -847,6 +847,29 @@
status = "disabled";
};

ethernet@40028000 {
reg = <0x40028000 0x8000>;
compatible = "st,stm32-ethernet-controller";
clock-names = "stm-eth";
clocks = <&rcc STM32_CLOCK(AHB1, 15)>;

mac: ethernet {
compatible = "st,stm32h7-ethernet", "st,stm32-ethernet";
interrupts = <92 0>;
clock-names = "mac-clk-tx", "mac-clk-rx";
clocks = <&rcc STM32_CLOCK(AHB1, 16)>,
<&rcc STM32_CLOCK(AHB1, 17)>;
status = "disabled";
};

mdio: mdio {
compatible = "st,stm32-mdio";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};

usbotg_fs: usb@40080000 {
compatible = "st,stm32-otgfs";
reg = <0x40080000 0x40000>;
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1 change: 1 addition & 0 deletions soc/st/stm32/stm32h7rsx/CMakeLists.txt
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Expand Up @@ -6,6 +6,7 @@ zephyr_sources(
)

zephyr_sources(mpu_regions.c)
zephyr_linker_sources(SECTIONS sections.ld)

zephyr_include_directories(.)

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14 changes: 14 additions & 0 deletions soc/st/stm32/stm32h7rsx/mpu_regions.c
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Expand Up @@ -26,6 +26,20 @@ static const struct arm_mpu_region mpu_regions[] = {

/* Region 3 */
MPU_REGION_ENTRY("SRAM_0", CONFIG_SRAM_BASE_ADDRESS, REGION_RAM_ATTR(REGION_SRAM_SIZE)),

/* Region 4 - Ready only flash with unique device id */
MPU_REGION_ENTRY("ID", 0x08FFF800, REGION_FLASH_ATTR(REGION_2K)),
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@djiatsaf-st Can you confirm this is ok with you wrt #97731 ?
I guess name could be either but size may be adapted ?

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I confirm that it works well

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@TD-JBL TD-JBL Oct 17, 2025 •
edited
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Please also read my comment on PR #97731 about MPU configuration issues between this two PRs

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@TD-JBL Comment is not visible.

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@TD-JBL TD-JBL Oct 17, 2025 •
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My comment has a pending note next to it. Not sure for what it is waiting for. I'm not yet very familiar with the GitHub user interface....

I quote my comment from the other PR:

My PR #97364 most likely gets a problem with adding the memory attribute to sram2, because the order of MPU region initialization (see arm_mpu.c):

  1. elements from mpu_regions.c
  2. entries from the device tree with zephyr,memory-attr property
  3. entries resulting from CONFIG_USERSPACE, CONFIG_NOCACHE_MEMORY etc
  4. dynamic entries

As later defined regions overlapping earlier ones have a higher priority (called region overlay), the ATTR_MPU_RAM from dt will overlay the REGION_RAM_NOCACHE_ATTR / REGION_PPB_ATTR from my PR's mpu_regions.c. Never tried to overlay a smaller region with a bigger one, so maybe this is even illegal? Anyway, I need to figure a way to define my DMA memory regions after it is configured as standard memory.

I see the point of this change (and use it in my custom boards dts for other mem nodes), but how can I solve this?

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Not sure for what it is waiting for.

You need to submit your review (green button in the upper right)


#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(mac))
#define sram_eth_node DT_NODELABEL(sram2)
#if DT_NODE_HAS_STATUS_OKAY(sram_eth_node)
/* Region 5 - Ethernet DMA buffer RAM */
MPU_REGION_ENTRY("SRAM_ETH_BUF", DT_REG_ADDR(sram_eth_node),
REGION_RAM_NOCACHE_ATTR(REGION_16K)),
/* Region 6 - Ethernet DMA descriptor RAM (overlays the first 256B of SRAM_ETH_BUF)*/
MPU_REGION_ENTRY("SRAM_ETH_DESC", DT_REG_ADDR(sram_eth_node), REGION_PPB_ATTR(REGION_256B)),
#endif
#endif
};

const struct arm_mpu_config mpu_config = {
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20 changes: 20 additions & 0 deletions soc/st/stm32/stm32h7rsx/sections.ld
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@@ -0,0 +1,20 @@
/*
* Copyright (c) 2020 Mario Jaun
*
* SPDX-License-Identifier: Apache-2.0
*/

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(mac))
#define sram_eth_node DT_NODELABEL(sram2)
#if DT_NODE_HAS_STATUS_OKAY(sram_eth_node)
SECTION_DATA_PROLOGUE(eth_stm32,(NOLOAD),)
{
. = ABSOLUTE(DT_REG_ADDR(sram_eth_node));
*(.eth_stm32_desc)
. = ABSOLUTE(DT_REG_ADDR(sram_eth_node)) + 256;
*(.eth_stm32_buf)
. = ABSOLUTE(DT_REG_ADDR(sram_eth_node)) + 16K;
} GROUP_DATA_LINK_IN(LINKER_DT_NODE_REGION_NAME(sram_eth_node), LINKER_DT_NODE_REGION_NAME(sram_eth_node))
#endif /* DT_NODE_HAS_STATUS_OKAY(sram_eth_node) */

#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(mac)) */