drivers: flash: mcux-flexspi-nor: Support octal mode

[pdgendt]

Add support for JEDEC octal mode.

Disclaimer: this code is AI-assisted

Fixes #99496

After applying changes from #99421 I get the following results

# before
uart:~$ flash read_test is25wx01g@0 0 0x1000 10
Loop #1 done in 200371 ns.
Loop #2 done in 26416 ns.
Loop #3 done in 29667 ns.
Loop #4 done in 44531 ns.
Loop #5 done in 14257 ns.
Loop #6 done in 13775 ns.
Loop #7 done in 8481 ns.
Loop #8 done in 24797 ns.
Loop #9 done in 8652 ns.
Loop #10 done in 13571 ns.
Total: 384523 ns, Per loop: 38452 ns, Speed: ~101.6MiBps

# after
uart:~$ flash read_test is25wx01g@0 0 0x1000 10
Loop #1 done in 13607 ns.
Loop #2 done in 4619 ns.
Loop #3 done in 4310 ns.
Loop #4 done in 6263 ns.
Loop #5 done in 8767 ns.
Loop #6 done in 4126 ns.
Loop #7 done in 4126 ns.
Loop #8 done in 4126 ns.
Loop #9 done in 4120 ns.
Loop #10 done in 4126 ns.
Total: 58196 ns, Per loop: 5819 ns, Speed: ~671.3MiBps

[Copilot]

Pull Request Overview

This PR adds support for JEDEC octal mode (1-8-8) to the FlexSPI NOR flash driver, enabling significantly faster read speeds (~671 MiBps vs ~101 MiBps). The implementation reads SFDP DW19 to determine octal enable requirements and implements the S2B3 method (Status Register 2, Bit 3) for enabling octal mode.

• Adds parsing of JESD216 DW19 to detect octal enable requirements
• Implements octal enable sequence for S2B3 method (Status Register 2, Bit 3)
• Configures 1-8-8 read mode when supported by the flash device

---

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[Copilot]

These constants represent JESD216 DW19 Octal Enable Requirements but lack documentation explaining their purpose and origin. Consider adding a comment block explaining that these are bit field values from JESD216 SFDP DW19 bits [22:20] for Octal Enable Requirements, where 000b = no command needed, 001b = set bit 3 of Status Register 2, etc.

Suggested change

	/*
	* These constants represent the Octal Enable Requirement (OER) field values
	* from the JESD216 Serial Flash Discoverable Parameters (SFDP) standard,
	* specifically DW19 bits [22:20]. The OER field indicates what (if any)
	* command or register modification is required to enable Octal mode.
	* 000b = No command needed to enable Octal mode
	* 001b = Set bit 3 of Status Register 2 to enable Octal mode
	* (Other values may be defined in the standard for other requirements)
	*/

[Copilot]

The magic number 0x65 appears to be a Read Register command but is not defined as a named constant like other SPI NOR commands (e.g., SPI_NOR_CMD_WRSR2 on line 775). Consider defining this as a named constant such as SPI_NOR_CMD_RDREG or similar to improve code readability and maintainability.

[Copilot]

The magic number 0x02 as deviceAddress appears to be a register address for reading Status Register 2, but lacks explanation. Consider adding a comment or defining this as a named constant like SR2_ADDRESS or STATUS_REG2_ADDR to clarify its purpose.

[Copilot]

The magic numbers 0x08 (dummy cycles/bits) appears twice in this function (lines 770, 772) without explanation. Consider defining these as named constants or adding comments to explain why 8 dummy cycles are required for this specific read register command.

[Copilot]

This check verifies if bit 3 of Status Register 2 is already set (indicating octal mode is already enabled), but lacks a comment explaining this. Consider adding a comment like '/* Check if octal mode is already enabled (SR2 bit 3) */' to improve code clarity.

Suggested change

	/* Check if octal mode is already enabled (SR2 bit 3) */

[Copilot]

This line sets bit 3 to enable octal mode but lacks a comment explaining the purpose. Consider adding a comment like '/* Set bit 3 to enable octal mode */' to improve code clarity.

Suggested change

	/* Set bit 3 to enable octal mode */

[ZhaoxiangJin]

CC @Albort12138, @SuperHeroAbner

[Albort12138]

Can we move this to jesd216.h?

[pdgendt]

I've added some dw19 decode struct/function instead.

[sonarqubecloud]

Quality Gate passed

Issues
1 New issue
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

[pdgendt]

Adding DNM, this appears to do "something", but not enable octal mode, investigating.

[pdgendt]

It appears that 1-8-8 mode does get activated, haven't been able to verify HW that uses the octal enable requirement bit, as I don't have that.

It would be nice if vendors with access to JEDEC specs could review/test, thanks.