drivers: can: mcux: flexcan: fix prop_seg for enhanced bit timing #99844
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Move the FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG conditional logic from the general timing configuration to only apply within the CAN FD specific sections. This ensures that for classic CAN mode, prop_seg is always decremented by 1 regardless of the enhanced bit timing register feature. The previous implementation incorrectly applied the enhanced bit timing logic to classic CAN mode, which could cause timing misconfiguration on devices with enhanced bit timing register support when operating in classic CAN mode. Fixes zephyrproject-rtos#99746 Signed-off-by: William Tang <william.tang@nxp.com>
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str4t0m
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board test pass on v4.3.0-721-gc4b3b580816 |
henrikbrixandersen
requested changes
Nov 24, 2025
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| #endif /* CONFIG_CAN_MCUX_FLEXCAN_FD */ | ||
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| FLEXCAN_SetTimingConfig(base, &timing); |
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Why was this moved? Looks like the data phase timing is now applied to the arbitration phase as well?
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Move the FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG conditional logic from the general timing configuration to only apply within the CAN FD specific sections.
This ensures that for classic CAN mode, prop_seg is always decremented by 1 regardless of the enhanced bit timing register feature.
The previous implementation incorrectly applied the enhanced bit timing logic to classic CAN mode, which could cause timing misconfiguration on devices with enhanced bit timing register support when operating in classic CAN mode.
Fixes #99746