Now gem5-HDL has been included in a complete and latest project named PAAS. In that project, more interesting features of state-of-art CPU-FPGA system are implemented and detailed manual is provided. More details of the structure and implementation of PAAS can be found in the paper PAAS: A system level simulator for heterogeneous computing architectures.
gem5-HDL make the simulation of CPU-FPGA system much easier because it realize the communication between C/C++ and Verilog in the heterogeneous system. This project is nearly finished, thanks to Prof. Wei ZHANG, Liang FENG and Sinha Sharad's help.
If you have problems in using gem5-HDL, please feel free to send a email to tliang@ust.hk.
We are glad if this simulator will help your project. Please make the citation when you apply gem5-HDL in your work which will be published.
Tingyuan Liang RCSL, ECE, HKUST