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sashakatne/README.md
  • 👋 Hi, I’m @sashakatne
  • 👀 I’m interested in: Exploring the fascinating world of computer engineering, especially the synergy between hardware and software. I am passionate about AI-enhanced silicon design, pre-silicon validation, and computer architecture. My goal is to innovate and optimize how software interacts with hardware.
  • 🌱 I’m currently learning: Delving deep into the intricacies of System Verilog, Microprocessor System Design, Computer Architecture, and the fundamentals of Pre-Silicon Validation. Additionally, I am enhancing my skills in Python and other computational tools to bolster my software development expertise.
  • 🤝 I’m looking to collaborate on: Exciting projects that involve hardware-software integration, AI-enhanced design, and any initiatives that push the boundaries of current technology. If you're working on something cutting-edge in these fields, I'd love to connect and contribute!
  • 📫 How to reach me: Feel free to connect with me on LinkedIn (https://www.linkedin.com/in/yashaswikatne/). I'm always open to discussions, collaborations, and new opportunities.
  • ⚡ Fun fact: When I'm not immersed in code or hardware schematics, you'll likely find me exploring the beautiful hiking trails of Portland or experimenting with new recipes in my kitchen. I believe in maintaining a balance between rigorous academics and rejuvenating hobbies!

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  1. nvfp4-dotprod-formal-dv nvfp4-dotprod-formal-dv Public

    Formal (VC Formal FPV) and UVM verification of an 8-lane mixed-precision INT8/BF16/NVFP4 dot-product core, with a shared SystemVerilog golden reference across assertions and scoreboards.

    SystemVerilog 1

  2. FV_AHB2APB FV_AHB2APB Public

    Formal verification (Synopsys VC Formal FPV/AEP) of a synchronous AMBA AHB-to-APB bridge — SVA assertions, bind files, bug-injection regressions, and a directed-simulation sanity check, with a form…

    SystemVerilog

  3. Split-L1-Cache-simulator Split-L1-Cache-simulator Public

    A C++ simulator for a 32-bit split-L1 cache (separate I/D) with MESI coherence, pseudo-LRU replacement, and write-back/write-allocate policy — reads a trace and reports hit/miss statistics or per-o…

    C++

  4. SystemVerilog_Playground SystemVerilog_Playground Public

    A personal SystemVerilog playground of RTL design and verification experiments — arbiters, ALUs (conventional/class-based/UVM), multipliers, FSM controllers, and floating-point classes — plus a 17-…

    SystemVerilog

  5. Team3_AsyncFIFO_S24_ECE593 Team3_AsyncFIFO_S24_ECE593 Public

    Design and UVM verification of a 64-entry 8-bit asynchronous FIFO for clock-domain crossing (80 MHz write / 50 MHz read) — Gray-coded pointers, two-flop synchronizers, wrap-aware full/empty flags, …

    SystemVerilog