⚡ Static Timing Analyzer (Mini STA)

A C++ project to simulate Static Timing Analysis for digital circuits. This tool helps determine the critical path, arrival times, and total delays in a given logic netlist.

---

🧠 What is STA?

Static Timing Analysis (STA) is a method used in digital circuit design to ensure signal timing requirements are met without simulating all input combinations. It works by calculating arrival times at each gate and identifying the longest (critical) path in the circuit.

---

📦 Features

• ✅ Load netlist from a .txt file
• ⏱️ Compute arrival times and total path delays
• 🚨 Identify critical paths
• 🖨️ Export results to a readable output file
• 📊 Visualize the circuit using Graphviz

---

🛠️ Sample Netlist Format

Each line represents a gate or input like this: INPUT IN1 0 INPUT IN2 0 IN1 G1 5 IN2 G1 3 G1 G2 4 G2 OUT 7 IN1 G3 2 G3 OUT 6

INPUT X D — declares input X with delay D

• X Y D — edge from node X to node Y with delay D

---

🚀 How to Run

1. Compile

   g++ main.cpp graph.cpp -o main

2. ./main
3. visualize dot -Tpng output.dot -o circuit.png