Nonce space configuration

[adammwest]

#65

Currently mujina uses default register values meaning you get less than 100% of the nonce space

Version rolling chips
BM1398/62/66/68/70

For the version rolling BM series (Antminer Chips) the default register values encode some amount of chips in a chain
so when you use those default values with a smaller chain you get a fraction of the nonce space.
Another detail is changing the frequency changes the nonce space which in Unintuative

This is relavent for SV2 and header only mining, here the miner mines with the nonce+version space, which means
only up to a device with 2^48 ~ 280Ths are supported. The 280Ths assumes full nonce space.

This is relatively well understood (apart from the 1373) but its in C and C++

• bitaxes functions to control nonce space and timeouts for all chip topologies bitaxeorg/ESP-Miner#420
• nerdaxe Draft: control nonce space and timeouts for all all chip topologies shufps/ESP-Miner-NerdQAxePlus#546

Questions

1. should the bm chips in mujina be reconfigured at something close to 100% or some other value of the nonce space
2. for other chips like BZM this may not be applicable, what happens there

[jayrmotta]

Questions

1. should the bm chips in mujina be reconfigured at something close to 100% or some other value of the nonce space

I'm not sure I understand the question @adammwest. It seems to me the answer is yes, covering 100% of the nonce space is desirable. But perhaps you're asking that for another reason?

[adammwest]

I was assessing the interest by opening a discussion, rather than going straight to PR as per #7
I also think its desirable

[rkuester]

Hey @adammwest, thanks for sharing this with us over here in Mujina! I’m keen to get a better grasp of how that register works and how the search space behaves. I’m swamped with a conference and travel at the moment, but I’m excited to look into this and reply when I get back.

[rkuester]

Following up on this: I've now spent serious time in both reference implementations, ESP-Miner PR 420 and its NerdQAxePlus port, PR 546, including the code, the review threads, and the duplicate-share investigations run during review, and cross-checked what I found against factory firmware captures from S21 Pro and S19j Pro chains. I'm in the middle of distilling it all into mujina's BM13xx protocol doc; the draft lives on my working branch under Search Space Distribution. Fair warning: it's a little long at the moment because it records all my questions and musings along the way; I'm distilling it down as questions get answered, so details will shift.

More to come as the doc firms up; happy to dig into any of it here in the meantime.