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IAR LDR{,B,H}T fix#242

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JonatanAntoni merged 1 commit intoARM-software:mainfrom
RobinKastberg:iar-ldrt
Jun 16, 2025
Merged

IAR LDR{,B,H}T fix#242
JonatanAntoni merged 1 commit intoARM-software:mainfrom
RobinKastberg:iar-ldrt

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Inline assembler constraints were incorrect.

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github-actions Bot commented Jun 16, 2025

Test Results

   264 files   -   108     264 suites   - 108   0s ⏱️ - 8m 25s
    56 tests +    7      54 ✅ + 10      2 💤  -     3  0 ❌ ±0 
14 292 runs   - 3 936  12 124 ✅ +160  2 168 💤  - 4 096  0 ❌ ±0 

Results for commit 456dc6f. ± Comparison against base commit 0fa5d9f.

This pull request removes 49 and adds 56 tests. Note that renamed tests count towards both.
CMSIS-Core.src ‑ apsr.c
CMSIS-Core.src ‑ basepri.c
CMSIS-Core.src ‑ bkpt.c
CMSIS-Core.src ‑ clrex.c
CMSIS-Core.src ‑ clz.c
CMSIS-Core.src ‑ control.c
CMSIS-Core.src ‑ cp15.c
CMSIS-Core.src ‑ cpsr.c
CMSIS-Core.src ‑ dmb.c
CMSIS-Core.src ‑ dsb.c
…
TC_CML1Cache_CleanDCacheByAddrWhileDisabled
TC_CML1Cache_EnDisableDCache
TC_CML1Cache_EnDisableICache
TC_CoreFunc_APSR
TC_CoreFunc_BASEPRI
TC_CoreFunc_Control
TC_CoreFunc_EnDisIRQ
TC_CoreFunc_EncDecIRQPrio
TC_CoreFunc_FAULTMASK
TC_CoreFunc_FPSCR
…
This pull request removes 5 skipped tests and adds 2 skipped tests. Note that renamed tests count towards both.
CMSIS-Core.src ‑ lda.c
CMSIS-Core.src ‑ ldaex.c
CMSIS-Core.src ‑ stl.c
CMSIS-Core.src ‑ stlex.c
CMSIS-Core.src ‑ systick.c
TC_CoreInstr_WFE
TC_CoreInstr_WFI

♻️ This comment has been updated with latest results.

Inline assembler constraints were incorrect.

Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
@JonatanAntoni JonatanAntoni merged commit 6f0a58d into ARM-software:main Jun 16, 2025
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@RobinKastberg
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@JonatanAntoni I think this issue affects the other toolchains as well.. just that they got more luck with register allocation. however I hadnt set up the others to test with. Maybe worth a look?

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JonatanAntoni commented Jun 16, 2025

@RobinKastberg, any chance to detect issues like this in a test? E.g., by inspecting the assembly output (disassembly) as done in the Core tests using lit?

I.e., you added ampersand output operand (=&). I read this as a specific instruction to the compiler to not reuse the input register for output value. I am far from being an compiler expert to tell if this is required or compilers may be clever enough.

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@RobinKastberg, any chance to detect issues like this in a test? E.g., by inspecting the assembly output (disassembly) as done in the Core tests using lit?

I.e., you added ampersand output operand (=&). I read this as a specific instruction to the compiler to not reuse the input register for output value. I am far from being an compiler expert to tell if this is required or compilers may be clever enough.

If you can trigger it you will get a compilation/assemblation error and dont need a test (I would assume, haven't checked) The hard part is making the compiler register allocation put the input register into the same register as output. And if we try too hard we will succeed and the compilation will fail. Maybe there is some happy middle ground.

I can experiment a bit.

tpambor pushed a commit to tpambor/CMSIS_6 that referenced this pull request Jun 20, 2025
Inline assembler constraints were incorrect.

Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
wearyzen pushed a commit to zephyrproject-rtos/CMSIS_6 that referenced this pull request Jun 23, 2025
Inline assembler constraints were incorrect.

Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
wearyzen added a commit to zephyrproject-rtos/CMSIS_6 that referenced this pull request Jun 23, 2025
wearyzen added a commit to zephyrproject-rtos/CMSIS_6 that referenced this pull request Jun 23, 2025
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2 participants