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Add missing CPPWR definitions#243

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JonatanAntoni merged 1 commit intoARM-software:mainfrom
david-hazi-arm:dev/davhaz01/cppwr_fix
Jun 23, 2025
Merged

Add missing CPPWR definitions#243
JonatanAntoni merged 1 commit intoARM-software:mainfrom
david-hazi-arm:dev/davhaz01/cppwr_fix

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Added missing Coprocessor Power Control Register Definitions to the v8m-mainline cpus.

Added missing Coprocessor Power Control Register Definitions
to the v8m-mainline cpus.

Signed-off-by: Dávid Házi <david.hazi@arm.com>
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Test Results

   264 files   -   108     264 suites   - 108   0s ⏱️ - 8m 28s
    56 tests +    7      54 ✅ + 10      2 💤  -     3  0 ❌ ±0 
14 292 runs   - 3 936  12 124 ✅ +160  2 168 💤  - 4 096  0 ❌ ±0 

Results for commit dbf0888. ± Comparison against base commit 6f0a58d.

This pull request removes 49 and adds 56 tests. Note that renamed tests count towards both.
CMSIS-Core.src ‑ apsr.c
CMSIS-Core.src ‑ basepri.c
CMSIS-Core.src ‑ bkpt.c
CMSIS-Core.src ‑ clrex.c
CMSIS-Core.src ‑ clz.c
CMSIS-Core.src ‑ control.c
CMSIS-Core.src ‑ cp15.c
CMSIS-Core.src ‑ cpsr.c
CMSIS-Core.src ‑ dmb.c
CMSIS-Core.src ‑ dsb.c
…
TC_CML1Cache_CleanDCacheByAddrWhileDisabled
TC_CML1Cache_EnDisableDCache
TC_CML1Cache_EnDisableICache
TC_CoreFunc_APSR
TC_CoreFunc_BASEPRI
TC_CoreFunc_Control
TC_CoreFunc_EnDisIRQ
TC_CoreFunc_EncDecIRQPrio
TC_CoreFunc_FAULTMASK
TC_CoreFunc_FPSCR
…
This pull request removes 5 skipped tests and adds 2 skipped tests. Note that renamed tests count towards both.
CMSIS-Core.src ‑ lda.c
CMSIS-Core.src ‑ ldaex.c
CMSIS-Core.src ‑ stl.c
CMSIS-Core.src ‑ stlex.c
CMSIS-Core.src ‑ systick.c
TC_CoreInstr_WFE
TC_CoreInstr_WFI

@JonatanAntoni JonatanAntoni requested a review from Copilot June 23, 2025 06:27
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Pull Request Overview

This PR adds missing Coprocessor Power Control Register (CPPWR) bit definitions for SUS10/SU10 and SUS11/SU11 across several v8m‐mainline CPU headers and updates copyright years.

  • Bumped Arm Limited copyright years from 2024 to 2025.
  • Introduced *_CPPWR_SUS11_Pos, *_CPPWR_SU11_Pos, *_CPPWR_SUS10_Pos, and corresponding masks in four core headers.

Reviewed Changes

Copilot reviewed 4 out of 4 changed files in this pull request and generated 1 comment.

File Description
CMSIS/Core/Include/core_starmc1.h Updated copyright year; added SCnSCB CPPWR SUS/SU bit definitions.
CMSIS/Core/Include/core_cm52.h Updated copyright year; added ICB CPPWR SUS/SU bit definitions.
CMSIS/Core/Include/core_cm35p.h Updated copyright year; added SCnSCB CPPWR SUS/SU bit definitions.
CMSIS/Core/Include/core_cm33.h Updated copyright year; added SCnSCB CPPWR SUS/SU bit definitions.
Comments suppressed due to low confidence (2)

CMSIS/Core/Include/core_cm52.h:2

  • For consistency, consider bumping the second copyright year for Arm Technology (China) Co., Ltd. from 2024 to 2025.
 * Copyright (c) 2018-2025 Arm Limited. Copyright (c) 2024 Arm Technology (China) Co., Ltd. All rights reserved.

CMSIS/Core/Include/core_cm52.h:1079

  • There are no tests or static assertions validating these new bit positions and masks; adding coverage will help catch mismatches against the hardware specification.
#define ICB_CPPWR_SUS11_Pos             23U                                               /*!< CPPWR: SUS11 Position */

Comment thread CMSIS/Core/Include/core_cm52.h
@JonatanAntoni JonatanAntoni merged commit 964440d into ARM-software:main Jun 23, 2025
8 checks passed
valeriosetti pushed a commit to valeriosetti/CMSIS_6 that referenced this pull request Apr 27, 2026
Added missing Coprocessor Power Control Register Definitions to the
v8m-mainline cpus.

Signed-off-by: Dávid Házi <david.hazi@arm.com>
valeriosetti pushed a commit to valeriosetti/CMSIS_6 that referenced this pull request Apr 27, 2026
Added missing Coprocessor Power Control Register Definitions to the
v8m-mainline cpus.

Signed-off-by: Dávid Házi <david.hazi@arm.com>
valeriosetti pushed a commit to valeriosetti/CMSIS_6 that referenced this pull request Apr 29, 2026
Added missing Coprocessor Power Control Register Definitions to the
v8m-mainline cpus.

Signed-off-by: Dávid Házi <david.hazi@arm.com>
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3 participants