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Merge osq_lock from integration to master #29

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Merged
merged 19 commits into from
Jun 8, 2018
Merged

Merge osq_lock from integration to master #29

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8c5d672
Merge pull request #1 from ARM-software/master
zoybai May 22, 2018
fb20b14
Add linux kernel osq_lock to lockhammer test
May 24, 2018
e1ffe17
Merge branch 'integration' into lh_osq_lock
zoybai May 24, 2018
a6f4748
Update Makefile
zoybai May 24, 2018
79b9252
Use threadnum instead of sched_getcpu() to determine the core num
zoybai May 24, 2018
dc5b721
Merge branch 'lh_osq_lock' of https://github.com/zoybai/synchronizati…
May 30, 2018
9ccabcc
Merge branch 'lh_osq_lock' of https://github.com/zoybai/synchronizati…
May 30, 2018
aeae748
Merge branch 'lh_osq_lock' of https://github.com/zoybai/synchronizati…
May 30, 2018
7f53bcc
Merge branch 'lh_osq_lock' of https://github.com/zoybai/synchronizati…
May 30, 2018
cfd0571
Fixed cmpxchg llsc register bug for non-LSE aarch64
Jun 5, 2018
34d2be0
Fixed cmpxchg llsc register bug for non-LSE aarch64
Jun 5, 2018
6726408
Merge branch 'lh_osq_lock' of https://github.com/zoybai/synchronizati…
Jun 7, 2018
56fe3b0
Change default sleep to 0us
Jun 7, 2018
632fd1e
Add more comments for changes in lk_cmpxchg.h and osq_lock.h
Jun 7, 2018
8c33399
Merge pull request #24 from zoybai/lh_osq_lock
zoybai Jun 7, 2018
4f32ba4
Fixed osq_lock and tbb_spin_rw_mutex redefine warnings
Jun 7, 2018
d2b704b
Add detail introduction for osq_lock workload
Jun 8, 2018
ae08976
Add detail introduction for osq_lock workload
Jun 8, 2018
478677d
Merge branch 'integration' of https://github.com/ARM-software/synchro…
Jun 8, 2018
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6 changes: 5 additions & 1 deletion benchmarks/lockhammer/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,8 @@ TEST_TARGETS=lh_swap_mutex \
lh_queued_spinlock \
lh_empty \
lh_jvm_objectmonitor \
lh_tbb_spin_rw_mutex
lh_tbb_spin_rw_mutex \
lh_osq_lock

ifeq ($(TARGET_ARCH),aarch64)
TEST_TARGETS+=lh_hybrid_spinlock \
Expand All @@ -55,6 +56,9 @@ lh_hybrid_spinlock: ../../ext/linux/hybrid_spinlock.h include/atomics.h ../../ex
lh_hybrid_spinlock_fastdequeue: ../../ext/linux/hybrid_spinlock_fastdequeue.h include/atomics.h ../../ext/linux/include/lk_atomics.h src/lockhammer.c
${CC} ${CFLAGS} -DATOMIC_TEST=\"$<\" src/lockhammer.c -o build/$@ ${LDFLAGS}

lh_osq_lock: ../../ext/linux/osq_lock.h ../../ext/linux/include/lk_atomics.h ../../ext/linux/include/lk_barrier.h ../../ext/linux/include/lk_cmpxchg.h include/atomics.h src/lockhammer.c
${CC} ${CFLAGS} -DATOMIC_TEST=\"$<\" src/lockhammer.c -o build/$@ ${LDFLAGS}

lh_queued_spinlock: ../../ext/linux/queued_spinlock.h include/atomics.h ../../ext/linux/include/lk_atomics.h src/lockhammer.c
${CC} ${CFLAGS} -DATOMIC_TEST=\"$<\" src/lockhammer.c -o build/$@ ${LDFLAGS}

Expand Down
4 changes: 4 additions & 0 deletions ext/linux/include/lk_atomics.h
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Original file line number Diff line number Diff line change
Expand Up @@ -392,3 +392,7 @@ do { \

#define arch_mcs_spin_unlock_contended(l) \
smp_store_release((l), 1)

#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) READ_ONCE((v)->counter)
#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
52 changes: 52 additions & 0 deletions ext/linux/include/lk_barrier.h
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Original file line number Diff line number Diff line change
@@ -0,0 +1,52 @@
/* SPDX-License-Identifier: GPL-2.0 */

/* Based on Linux kernel 4.16.10
* arch/arm64/include/asm/barrier.h
* arch/x86/include/asm/barrier.h
* https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/?h=v4.16.10&id=b3fdf8284efbc5020dfbd0a28150637189076115
*/

#ifndef __ASM_BARRIER_H
#define __ASM_BARRIER_H

#include "lk_cmpxchg.h"

#if defined(__x86_64__)

#define mb() asm volatile("mfence":::"memory")
#define rmb() asm volatile("lfence":::"memory")
#define wmb() asm volatile("sfence" ::: "memory")
#define dma_rmb() barrier()
#define dma_wmb() barrier()
#define smp_mb() asm volatile("lock; addl $0,-4(%%rsp)" ::: "memory", "cc")
#define smp_rmb() dma_rmb()
#define smp_wmb() barrier()
#define smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)


/* Atomic operations are already serializing on x86 */
#define __smp_mb__before_atomic() barrier()
#define __smp_mb__after_atomic() barrier()


#elif defined(__aarch64__)

#define isb() asm volatile("isb" : : : "memory")
#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
#define psb_csync() asm volatile("hint #17" : : : "memory")
#define csdb() asm volatile("hint #20" : : : "memory")
#define mb() dsb(sy)
#define rmb() dsb(ld)
#define wmb() dsb(st)
#define dma_rmb() dmb(oshld)
#define dma_wmb() dmb(oshst)
#define smp_mb() dmb(ish)
#define smp_rmb() dmb(ishld)
#define smp_wmb() dmb(ishst)

#else /* No Arch */
/* TODO: No Arch Default */
#endif /* __x86_64__ */

#endif /* __ASM_BARRIER_H */
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